Iron vulnerability in DRAM allows altering the contents of someone else's memory

    Published article by Yoongu Kim & others. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors , which describes how to change the contents of DRAM memory that does not require access to this address. In fact, this means breaking memory isolation between processes or virtual machines. Of the 129 tested memory modules, 110 were vulnerable, including all modules released after 2012.


    DRAM Organization



    dram structure
    DRAM is a two-dimensional lattice, in the nodes of which there are memory cells, each of which stores one bit. Each cell consists of a transistor, and a capacitor, which can be charged or not charged, which corresponds to the value of bit 1 or 0. Capacitors lose charge over time, so it is necessary to periodically (several tens of milliseconds) rewrite information (regeneration). In modern chips, to improve performance, several independent modules (“banks”) are made, with separate output stages.

    To read information, a voltage is applied to one of the horizontal lines ( wordline ), so that the corresponding line of transistors opens. Moreover, with vertical lines ( bitline) the charges of the capacitors of the cells in this row are read. After that, the wordline is closed, which allows you to move on to reading another line.

    It turned out that if you turn the wordline on and off periodically , the induced currents lead to an increase in leakage in neighboring cells of the same bank, and if you make many switching between regeneration cycles, this may be enough to switch the bit from 0 to 1 or vice versa.

    Demonstration



    The effect can be achieved using code that does not require any special privileges. The simplest attack looks like this:

    code1a:
      mov (X), %eax  ; прочитать адрес X
      mov (Y), %ebx  ; прочитать адрес Y
      clflush (X)    ; сбросить строку кэша, соответствующую адресу X
      clflush (Y)    ; сбросить строку кэша, соответствующую адресу Y
      mfence         ; дождаться окончания операций с кэшем
      jmp code1a
    


    Addresses X and Y must be in the same bank, but in different DRAM lines. A cache reset is needed to ensure reads from RAM on every cycle. Two addresses must be used to ensure that wordline is turned on / off on each cycle. This code does not cause a vulnerability, since DRAM logic optimizes the inclusion of wordline, and the necessary constant switching does not occur:

    code1b:
      mov (X), %eax
      clflush (X)
      mfence
      jmp code1b
    


    To cause an error, it is necessary to do several hundred thousand cycles in the time between two regenerations (usually 64 ms), which is quite achievable. The presence of ECC does not help much, since errors are often common in several bits at the same time.

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