Physical layer implementation in switches

    Almost all of our switches are declared PHYless, which raises questions. What does this mean, what are the features that need to be taken into account?

    A range of up to 100 meters is available on twisted pair, optics can transmit from 300 meters using 10GBASE-SR to 80 kilometers using 10GBASE-ZR. The situation changes radically when a transition is made from external cables to printed circuit boards. Due to the enormous density of the signal lines, the range at which the signal remains intact is measured in inches.

    To communicate with the switching matrix (ASIC), SFP + ports use an electrical interface called SFI, and transceivers are optimized to minimize size and power consumption, there is no room for iron-quality signal. Modern switching ASICs (for example Broadcom Trident + and Intel Alta) are capable of receiving SFI signals directly from ports, switches with this port implementation are called PHYless. However, if the length of the tracks does not allow delivering the signal without distortion from the port to the matrix, an additional chip called PHY or SERDES is required.

    What is he doing?

    Significant signal distortion occurs with a long track length, one of the important functions of the chip is the compensation of this phenomenon, electronic dispersion compensation (EDC), which is necessary for the operation of 10GBASE-LRM and 10GBASE-ER. A number of other tasks are also performed:

    1. Convert electrical interfaces (e.g. SFI to XFI, or SFI to KR).
    2. SERDES - Serial / Parallel conversion (for example, one SFI line to four XAUI lines).
    3. Restore signal integrity and re-timing.
    4. Physical layer features such as Physical Coding Sublayer (PCS).

    A summary table of the capabilities of various types of physical layer implementations in switches:

    EDC PHYLite PHYRetimerPhyless
    Clock Recovery (Retiming)XXX
    Singal conversion (ex. XLPPI / KR4 <-> XLAUI, XFI <-> SFI) XX
    Auto Gain Control (Regeneration for amplitude control)X
    Microcontroller and dsp integratedX
    EDC for LRMX
    Roundtrip Latency (40nm, CMOS from BRCM)50 ~ 70ns5ns<5ns0ns
    Power Consumption (40nm, COMS from BRCM)500 ~ 700mw / 10G port300mw / 10GE port<300mw / 10GE port0mw
    Additional Features
    IEEE 1588X
    Sync. EthernetX
    ApplicationDSP based EDC PHY. Drive SFP +, QSFP + Modules and Backplanes. Supports 10GBASE-LRM / MACsec / 1588 / FCoEDrive SFP +, QSFP + Modules and BackplanesSimplex and Duplex Equalizers for Front / Backplane & Chip-2-Chip applications

    Using an example of a switch with 48 10G SFP + ports and 4 40G QSFP + ports ( Eos 400 and similar with EDC PHY), advantages and disadvantages can be derived:

    1. Reduced power consumption by 61W (240W -> 179W).
    2. Delay reduction by 50-70ns.
    3. Increased MTBF and decreased MTTR.
    4. Significant price reduction

    1. SFP-10G-LRM (Long Reach Multi-mode) is not supported.
    2. You cannot implement an FCoE gateway (but it can work on an FCoE network).

    If you do not need to build a network with distances between nodes over 10 km, you do not need an FCoE gateway and accurate synchronization over the network, then the PHYless option is preferable. It costs less, consumes less, reliability is higher - what else is needed?

    The vast majority of tasks fit this framework :)

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