Temporal FPGA analysis or how I mastered Timequest

Original author: Altera support
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Good day, dear Khabravchians.

In fact, I am an engineer in radio physics and FPGA programming is not my direct activity, but at one point I needed to write a program to synchronize several oscillographic modules. I had to master this science. About what problems I had with this, under the cut.

Many I hope at least one of you programmed for FPGA at a level higher than blinking an LED. If this was the case, then you might notice that sometimes something does not work right. There are problems with timings of this kind: with an increase in frequency, the system becomes unstable, the bits begin to stick, the data disappears and the project does not work.

This is a paraphrase of an article about where these problems come from and how to deal with them. The author of the post uses ALTERA and software to develop the same company (Quartus II).

To better understand the essence of the problem, consider the simplest model of an 8-bit memory cell.

module habr111(
    input [7:0] data,
    input clk,
    output[7:0] out
reg [7:0] count;
always @ ( posedge clk  )
    count <= data;
    assign out = count;

We start the simulator and see that when the data arrives at the input in a certain phase relative to the clock signal, garbage data appears at the output.

The thing is that a D-trigger digital device is only a first approximation. That is, in fact, this is a set of analog transistors that have their own rise time. It happens that clock catches the moment when the signal grows to a transition voltage between 0 and 1. This is called a metastable state and what will be formed at the output is not obvious.

Each bit also has its own delay: some bits come earlier, some later. If the data switching occurs at the time of switching the clock, then due to the above effect, a mix of old and new bits goes to the output.

For the project to work correctly, you need to get rid of these effects. To do this, you must independently consider those very times. In Quartus II, the Timequest program does this. The question is: why do we need to know this?

The scheme by which timeqwest calculates timings consists of two registers. If all of their parameters are known, she will calculate and make the correct wiring. But if there is a certain external register about which Timequest has no information, then the developer needs to calculate and enter everything on his own. How this is done is described in this article.

My free translation .

I hope this helps someone just as it helped me.

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