As I did not prepare and held a Rosnanov seminar on FPGAs in Moscow. Plans to do the same in Las Vegas and Zelenograd

    You have this dream: you find yourself on an exam or speak in front of a certain audience, and suddenly you realize that you weren’t preparing at all and now you’ll have to improvise. It was in this situation, but not in a dream, but in real life, that I faced the May holidays in Moscow, where I flew from California to conduct a three-day seminar for carefully selected students from leading Moscow physics schools. Under the auspices of RUSNANO, in the RUT gymnasium (MIIT) and in the presence of teachers from MIET, MIREA, MEPhI, MPEI and HSE MIEM.

    My Moscow colleagues hoped for me, and theoretically I should have brought along step-by-step instructions and examples of various exercises on a circuit board with a reconfigurable logic microcircuit. Actually, I had a bunch of some examples for other boards, of which I did not build anything in the clutter of flights and other events.

    Therefore, I took a universal example, which I wrote a year and a half ago, sitting on an Alma-Ata-Astana plane, threw out all the insides from the example, and began to fill it with schoolchildren without a hard plan. And oddly enough - it worked. In the process of filling, instructive moments of digital circuitry and the Verilog hardware description language arose, which during planning would not have arisen.

    On June 4, I and my colleagues at Wave Computing will conduct a similar seminar in Las Vegas, but only for adults, and on July 8-19 I help MIET to conduct a summer school in Zelenograd. Plans for these events (not final, but for discussion in a group of teachers and engineers, including here on Habré) - at the end of the post.

    Why do we need a seminar on FPGAs for schoolchildren? Programmable logic integrated circuits (FPGAs or FPGAs - Field Programmable Gate Arrays) are a traditional way of consolidating knowledge in practice when studying the design of digital circuits at the level of register transfers using hardware description languages. In other words, the key technology for developing iPhones - microchips inside iPhones are designed that way. Russia's lag behind iPhones was also due to the fact that FPGA, microarchitecture, and hardware description languages ​​were introduced in Berkeley and MIT in the early 1990s, and in Russia due to the collapse of the USSR much later.

    The last Rosnanov seminar went surprisingly smoothly primarily because the students who came to it had previously completed a theoretical online course with a career-oriented survey of modern microcircuit design methods. The online course is intended for advanced schoolchildren of the olympiad type and consists of three modules: “From the transistor to the microcircuit” , “The logical side of digital circuitry” and “The physical side of digital circuitry”. In this course, students get acquainted with the so-called RTL2GDSII route - a group of technologies that engineers use in electronic companies to design bulk chips, Application Specific Integrated Circuits - ASIC. FPGAs / FPGAs are used to prototype ASICs, including companies such as Intel, Apple and NVidia.

    Since the students took the online course, they have already learned what D-trigger, state machine, logical synthesis and tracing are. They also saw the hardware description language in the online course. Now this knowledge, which lay passively in their memory, needed only to be revived.

    Now I will always for any seminars in the CIS countries (in addition to the seminars already planned, I have proposals to conduct this in Minsk, Sochi and Yakutsk) to set the condition for the host to pre-admit schoolchildren or students through three modules of the online course, since after only motivated people remain who have already gone through all the tedious aspects, and pure creativity remains for reinforcement, the last moment, such as the fall of an apple that hit Newton’s head. In addition, the online course links all this activity to adult professions, the next stage, draws a distant goal.

    In total, before flying to Moscow, I launched a universal example at my home in Sunnyvale, California. Example code :

    On the first day of the workshop, we practiced with microcircuits with a small degree of integration on a breadboard. This technology is 50 years old, but no one has come up with a better idea, in real life, than in simulation, of showing how D-triggers work, for example. Although it seems to many modern technology teachers in schools that this is outdated and unnecessary, but now in the 6.111 course of the Massachusetts Institute of Technology, now, in the academic year 2018/2019, the first lab on digital circuitry goes exactly this way with microcircuits with a small degree of integration - see http: // .

    In addition, using the example of connecting microcircuits with a small degree of integration with buttons, it is convenient to explain what it is, why it is needed, and how pull-up resistors work. And why they give a potential of 0 when the button is not pressed, and how is this related to the voltage divider.

    Even when, with the example of a microcircuit of a small degree of integration, the LED burns out, the students get life experience that it is necessary to put a resistor there. If they see this on a computer screen in a software simulator of a breadboard, they won’t get such a life experience, since you can draw anything on the screen and schoolchildren will not be sure that burnout is true.

    Here is how the function of the D-flip-flop is clearly visible on microcircuits of a small degree of integration:

    The second day began with a historical sketch: how microchips were designed 50 years ago and how it has changed twice since then. One of the revolutions was superimposed on the collapse of the USSR and this is the main technical reason why Russia does not have iPhones.

    At 8.45, the story of how the Soviet buoy spy, who monitored the movement of American ships, was caught in the oceans, and what this led to.

    On March 13, the story of how one blogger’s publication John Cooley displaced the entire global industry from VHDL to Verilog.

    On 16.10, the story of how Microsoft Windows lost to Linux as a platform for the work of chip designers.

    In this part - a demonstration of how to run a program for the synthesis of digital logic and firmware configuration in the FPGA. In two ways - by running a script under Linux and in an integrated graphical shell. Also a brief description of the contents of the demo. After this gallop across Europe, students sit down at the graphical shell and do simple exercises, starting with the AND-OR-NOT logic elements, the inputs of which are connected to the buttons, and the outputs to the LEDs. Something like that:

    module top (input [2:0] key, output [7:0] led);
        wire a = ~ key [0];  // Кнопка выдает 0, когда нажата, поэтому ее нужно инвертировать
        wire b = ~ key [1];
        wire c = a & b;
        assign led [0] = ~ c;  // Светодиод тоже горит, когда на входе 0 и его тоже нужно инвертировать

    In the process, two interesting questions arose immediately. Firstly, at first I myself forgot that both the buttons and the LEDs are inverted on this board. That is, when the button is pressed, then 0 on the wire, and when not pressed, then 1. And when 0 is fed to the LED, it is on, and when 1 is not on. If you do not know about inversion, then the logical element AND (led [0] = key [0] & key [1]) starts to behave like OR, and OR - like I. Laws of de Morgan in action! ~ (a & b) == ~ a | ~ b, as well as ~ (a | b) == ~ a & ~ b.

    But even after some schoolchildren corrected, this business still worked the other way around. Then I looked into their code and found that when they were rewriting the code that I wrote on the board, they thought that “~” (tilde) is “-” (minus).additional code, and also why for single-bit numbers (- 0) == 0 and (- 1) == 1, while (~ 0) == 1 and (~ 1) == 0. And also so that for multi-bit numbers in the additional code, calculate its negation, it is enough to invert it bitwise and add one: - a == ((~ a) + 1).

    Continuation - parts 2.3 , 2.4 , 2.5 .

    The whole lesson was held under Linux, more precisely under Lubuntu 18.04 with Intel FPGA Quartus II installed on it. Lubuntu was loaded with SSDs on which Intel FPGA Quartus II Lite Edition 18.1 was also installed. To boot from the SSD, you just need to plug it into the USB 3.0 port, turn on the computer and press F12. Then enter the menu and say “load from USB”.

    Although the synthesis software for FPGA is also available under Windows, Linux is good for two reasons:

    1. Linux is able to work on more weak computers than Windows. For example, I have a laptop with 2 gigabytes of memory, so Intel FPGA / Altera Quartus II for Windows lays down on it, and works fine under Linux.

    2. All adult developers of bulk chips at Apple, NVidia and other electronic companies use Linux, which runs the programs Synopsys Design Compiler, Synopsys IC Compiler, Synopsys VCS, Cadence IES, etc.

    Why is it better to do everything on bootable SSDs and not put them on computers in the classroom? Because installing software from FPGA companies is a rather dreary process, and around Altera Quartus or Xilinx Vivado you need to run with a tambourine, change files in / etc and install old 32-bit libraries for some components, in particular, for the free version of Mentor ModelSim. Some libraries have to be compiled from source codes. There are scripts from Stanislav Zhelnio that do it all automatically, but even with this script, installing everything on a computer will take a couple of hours.

    Why not do everything in virtual machines? For example with VirtualBox? We tried this at Moscow State University and other places, but glitches with USB pulling can occur there. A bootable SSD with Lubuntu looks like the best option.

    To prepare the SSD set for the workshop, you need to put everything on one SSD, and then clone it with such a command that allows you to immediately write to three SSDs from one:

    time sudo dcfldd if=/dev/sdb bs=1M of=/dev/sdc of=/dev/sdd of=/dev/sde

    Here you need to know that not all SSD enclosures support Linux, for example, Kingwin Data Star spoils disks. The correct enclosures are Orico and Eluteng.

    Also, I do not recommend trying to replace SSDs with simple, downloadable USB flash drives. Although it also works on USB sticks, some operations are incredibly slow, causing discomfort and irritation. But on loaded SSD drives with USB 3.0, everything flies faster than Linux on an internal hard drive.

    I also tried sticking a bootable SSD drive into the Apple Mac by pressing the Option key at boot time, but it didn't work out. Neither through USB 3.1 port, nor through 3.0. It seems that the Mac at boot does not want to understand either the Ext4 file system, or the partition table. Are there poppy drivers and linuxoids among my readers? It would be interesting to know what to do (besides the option to use VirtualBox or other virtual machines).

    Interestingly, only 2 students from the entire group used Linux before the seminar. This is very strange for me, since in the place of the Russian Ministry of Education I would transfer all Russian schools to Linux 10 years ago, when Ubuntu became user-friendly. In addition to Ubuntu, one could make a special Russian version of Linux for education. Windows is clogged with viruses, you need to pay royalties for it, why is Windows better than Linux for say Python programming school courses? Or will Google docs not be enough for schoolchildren, but Microsoft Word is needed? I just do not understand.

    Even the South Korean government decided in 2020 to switch to Linux .

    In any case, at my seminar, schoolchildren had no problems with Linux, although, as I said, most schoolchildren used it for the first time.

    At the beginning of the third day I was late because I was invited to give a lecture to the Russian branch of Samsung and the event dragged on for 3 hours (you can download the lecture slides: 1 , 2 , 3 and an article about part of the content ), after which I got hungry and only during eating buckwheat and olivier in Mumu (which I really miss in California) found that my lesson in the gymnasium would begin in 5 minutes.

    Then I called Alexander Silantiev from MIET and asked to start the lesson without me. On the previous day, students began to exercise with a seven-segment indicator, displaying one letter. Now, if you cross the output of one letter with a shift register, you can implement the output on a multi-bit dynamic seven-segment indicator, and at the same time, students will learn how to code sequential logic on veril.

    The plan was a success - when I entered the classroom, some schoolchildren were already running letters slowly on a dynamic indicator, and so that they merged into words, all that was needed was to raise the frequency of generating the enable signal (enable) for the shift register:

    Then I passed the floor to Stanislav Zhelnio sparf from IVA Technologies, and he briefly outlined how to move from simple logic blocks to a tiny but completely real processor (see posts by Stanislav on Habr and schoolMIPS on GitHub ):

    Continuation of the lecture by Stanislav Zhelnio The

    seminar was held at the Grammar School of the Russian University of Transport (MIIT). At the seminar and before it, Irina Grunicheva and Gleb Romanov (eNano) helped; Alexey Pereverzev, Alexander Silantiev and Yevgeny Primakov from MIET, Alexander Romanov from HSE MIEM and his students, Alexei Kochnov from NIIIS, League of Robots (, Pavel Kirichenko (ICST, Intel, author of books php? id = 201192 ), Yegor Kuzmin from the Institute of Applied Mathematics , Russian Academy of Sciences, Daria Krivoruchko, a schoolgirl from SUNTs, was at LYuP, Timofey Cherkasov (Academy of Digital Technologies of St. Petersburg, School of Engineering Thinking LNMO), Alexander Bakerenkov and Julia Shaltaeva from the Pre-University of MEPhI, Vladimir Vorontsov from MPEI, Evgeny Pevtsov from MIREA, Vitaliy Kravchenko from Nautekh, Arkady Poe Yakov and Sergey Pevchenko of MEI.

    Ruslan Tikhonov from Amperka brought components for exercises with microcircuits of a small degree of integration.

    Publisher Dmitry Movchan, from DMK Press, presented each participant with useful books - a thick comprehensive textbook by David Harris and Sarah Harris, Digital circuitry and computer architecture, and easy reading by A. Hideharu, Entertaining electronics. Digital circuits. Manga

    Maxim Maslov, affiliated with the Moscow Institute of Physics and Technology, came to the seminar and donated FPGA boards to summer schools (they used to say that in Russia there is little charity for education).

    What will be next? And then there will be two events that will expand and deepen what we did at the RTH Grammar School. July 8-26 will be the MIET summer school in Zelenograd. Here is a suggestion for her program. Her first two weeks consists of five parts:

    1. The basics of digital circuits on microcircuits of a small degree of integration.
    2. Simple exercises with combinational and sequential logic on the FPGA board.
    3. Using FPGAs to control the graphic display.
    4. The device and implementation of the simplest microprocessor on the FPGA.
    5. Individual projects for creating games a la simplified Angry Birds, both based on a finite state machine purely in the FPGA hardware, and with program control from the simplest processor synthesized in the FPGA.

    But before the school on June 4 there will be a seminar in Las Vegas, at which we will deal not with the school processor, but with the industrial one.

    A more detailed program in Zelenograd:

    Week 1. The basics of digital logic.

    Day 1. Microcircuits with a small degree of integration, exercises with combinatorial logic
    Day 2. Microcircuits with a small degree of integration, exercises with sequential logic
    Day 3. FPGA, exercises with buttons, switches, LED, seven-segment indicator
    Day 4. FPGA, output of geometric shapes on VGA
    Day 5. FPGA, finite state machine for Angry Birds

    Week 2. Processor

    Day 1. Programming in assembly language.
    Day 2. One-cycle schoolMIPS processor.
    Day 3. Interaction of the processor with the conclusion of geometric shapes on VGA.
    Day 4. Lecture about interruptions and multitasking. Individual project - a video game programmed on the processor with output to VGA.
    Day 5. Lecture about the conveyor. Competition of individual projects.

    Week 1. Day 1. Small-scale integrated circuits.

    1.1. Exercises with combinatorial logic.

    1.1.1. XOR logic element on CD4070, without buttons and pull-up registers - repeat the demonstration.

    1.1.2. XOR logic element, add buttons and pull-up registers - repeat the demonstration.

    1.1.3. Individual task - by datashit to build a demonstration of one of the logical elements AND / OR / NOT / XOR / NOR / NAND / XNOR, with two, three, four or eight inputs: CD4081, Quad 2-Input AND CD4071, Quad 2-Input OR CD4011, Quad 2-Input NAND CD4001, Quad 2-Input NOR CD4073, Triple 3-Input AND CD4025, Triple 3-Input NOR CD4082, Dual 4-Input AND CD4072, Dual 4-Input OR CD4012, Dual 4-Input NAND CD4002, 4-Input NOR CD4068, 8-input AND NAND CD4078, 8-Input NOR

    1.2. 7-segment indicator with a common cathode.

    1.2.1. Assemble on a breadboard with resistors, try individual segments.
    1.2.2. Combination with 7-segment indicator driver, CD4511, BCD to 7-Segment Latch Decoder.
    1.2.3. Option - indicator with a common anode. Combine with the inverter CD4069, Inverter.
    1.2.4. Option - add 4 buttons with pull-up resistors to the CD4511 input.

    1.3. Combinational logic blocks - an individual task at the end of the day or in the form of homework:

    1.3.1. CD4532, 8-Bit Priority Encoder
    1.3.2. CD4051, Single 8-Channel Analog Switch, used as digital decoder
    1.3.3. CD4051, Single 8-Channel Analog Switch, used as digital multiplexer
    1.3.4. CD4052, Dual 4-Channel Analog Switch, used as digital multiplexer
    1.3.5. CD4053, Triple 2-Channel Analog Switch, used as digital multiplexer
    1.3.6. CD4008, 4-Bit Combinational Adder
    1.3.7. CD4063, 4-Bit Digital Comparator
    1.3.8. CD4585, 4-Bit Digital Comparator

    At the end of the day, everyone shows who did what.

    Week 1. Day 2. Exercises with sequential logic.

    1.2.1. Assemble a clock generator based on 555 chip. Try different capacitors and resistances.

    1.2.2. D-trigger on chip CD4013, Dual D-Flip-Flop With Set-Reset.

    1.2.3. Individual project: Shift register based on CD4015, Dual 4 Bit Static Shift Register, serial-in, parallel-out. Shift register based on CD4035, 4-Stage Shift Register, parallel-in, parallel-out. Shift register based on CD4014, 8-Stage Shift Register, parallel-in, serial-out. Counter with LED output CD4029, Binary Decimal Up Down Counter. Counter with output to a 7-segment indicator through the driver. More complex is a combination of shift registers CD4035 (parallel-in, serial-out) with serial adder CD4038. It needs a CD4069 inverter. Prior to this, I will demonstrate the serial adder CD4032 without an inverter. More complex is a combination of shift registers CD4014 (parallel-in, serial-out) with serial adder CD4038. It needs a CD4069 inverter. Week 1. Day 3. FPGA, exercises with buttons, switches, LED, seven-segment indicator 1.3.1. A logical element in combinational logic is input from buttons, output to LEDs. 1.3.2. The output of one letter on a seven-segment indicator.

    1.3.3. The simplest multiplexer is the letter output depending on the key pressed. Implementation using the constructs "?", "If", "case".

    1.3.4. Shift register.

    1.3.5. The word is displayed on an eight-bit dynamic seven-segment indicator using a shift register.

    1.3.6. Individual project, perhaps homework for the weekend: Shapes on the LED matrix. Snake running on a seven-segment indicator. Sound frequency signal generation, sound organ. Input from a 16-button keyboard. Code lock - recognition of a key sequence by a state machine. Integration with a rangefinder sensor. Integration with angle encoder.

    Day 4. FPGA, output of geometric shapes to VGA
    Day 5. FPGA, finite state machine for Angry Birds

    Week 2. Processor

    Day 1. Programming in assembly language.
    Day 2. One-cycle schoolMIPS processor.
    Day 3. Interaction of the processor with the conclusion of geometric shapes on VGA.
    Day 4. Lecture about interruptions and multitasking. Individual project - a video game programmed on the processor with output to VGA.
    Day 5. Lecture about the conveyor. Competition of individual projects.

    Week 3. Programmable radio. The block program consists of three main parts:

    - the basics of electrodynamics and radio wave propagation (theoretical part);
    - The principle of operation of the transceiver path (theory and practice);
    - The basics of digital signal processing - filtering, spectral analysis (theory and practice).

    Day 1. Theoretical foundations of electrodynamics and radio wave propagation. The structural diagram of the transmission path, the functions of the components. Signals (harmonic, rectangular). Signal practice using NI Elvis.
    Day 2. Transferring signals to a high frequency. Mathematical justification for frequency transfer using Matlab. Practical exercise in frequency transfer using NI Datex.
    Day 3. Amplification and emission of signals. Practice using NI Datex. Demonstration of the directivity of the antennas.
    Day 4. Filtering the signal. Practice using NI Datex. Digital Signal Filtering in Matlab
    Day 5. Transferring signals to a low frequency. Practice using NI Datex. Summarizing the material covered, summing up.

    About the rest of the days of the school, more details will be in a separate post, after discussing this in the organizing committee of the summer school. If you want to participate in the summer school at MIET in Zelenograd as a student or instructor, the organizers have just posted the contacts and registration . If you are a schoolchild, then it’s important that by July you completely complete all three modules of the Rosnanov online course ( “From the transistor to the microcircuit” , “The logical side of digital circuitry” and “The physical side of digital circuitry”) The practice will be difficult, and we will not be able to stop to figure out which cycle the value is at the input or output of the D-trigger. This does not immediately fit in your head, but if you take an online course, it will be easier for you.

    Some details about the seminar in Las Vegas on June 4 :

    It doesn’t often happen that an engineering seminar, developed initially for Russia, and tested in Russia (including MIPT), Ukraine and Kazakhstan, then begins in Las Vegas, at an electronics design automation conference. In Russia and Ukraine it was called the MIPSfpga Workshop, and at the Design Automation Conference it was called the MIPS Open Developer Day. Come June 4 at the Embassy Suites by Hilton Convention Center at 3600 Paradise Road, Las Vegas, and you will take part in a show that students and teachers from Moscow State University, Moscow Institute of Physics and Technology, Moscow Engineering Physics Institute, Zelenograd MIET, St. Petersburg ITMO, Tomsk TSU, Kiev KPI, Almaty AlmaU and partially Nazarbayev University in Astana.

    MIPSfpga is a package that contains the processor core in Verilog source code, which you can change, add new instructions, observe the cache and pipeline operation, build multiprocessor systems, change software and hardware at the same time, etc. In the new version of the seminar, you will add a coprocessor to the processor to accelerate artificial intelligence algorithms.

    In addition, in the new version of the seminar we will show how to configure the kernel from the MIPS microAptiv UP package and insert it into the MIPSfpga binding. When configured, you can create exotic processor options, for example a processor with 16 sets of 32 registers. You can automatically switch these sets when entering an interrupt and thereby quickly change the context without saving / restoring the context from memory, which in ordinary RTOS takes about a thousand cycles.

    MIPSfpga is not intended to be injected into an object from absolute zero. For its fruitful use, it is necessary for the student to already know the basics of digital circuitry, be able to program in C and in assembler, and also present the concepts of microarchitecture - conveyor, pipeline conflicts, etc. This is what is being studied at schoolMIPS, which we use in Zelenograd.

    Here is a slide about the mechanism for adding instructions to the MIPS microAptiv UP processor:

    At a seminar in Las Vegas on June 4, and probably at a summer school for young electronic engineers, which will be held July 8-26 at MIET in Zelenograd, my daughter Elizabeth Panchul will help me (if she receives a visa on time). Since Elizabeth is a semi-Russian-semi-Russian / Ukrainian, she speaks only English. Therefore, Russian instructors (students or graduate students of the Moscow Institute of Physics and Technology, Moscow State University, etc. who are ready to help us with Elizabeth and the MIET in conducting the school) can learn the correct accent of English from her, and she from them - the basics of Russian. In addition to studying Verilog, MIPS, architecture, microarchitecture and organizing DMA in memory when displaying on a graphic screen:

    We are waiting for you at all seminars, as well as in committees for creating their programs!

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    What aspects of schools in Moscow, Las Vegas and Zelenograd are you most interested in?

    • 52.6% Career guidance course from RUSNANO along the development route of modern electronics 10
    • 47.3% Exercises on the basics of digital logic on microcircuits of small degree of integration 9
    • 63.1% Exercises on the basics of designing combinational and sequential circuits on FPGA 12
    • 42.1% Exercises to display images and sprites on a graphic display 8
    • 42.1% Individual projects with purely circuitry implementation of graphic games with a state machine 8
    • 36.8% Individual projects with the implementation of games by a combination of a soft core program and a VGA controller in FPGA 7
    • 78.9% Exercises with an industrial processor synthesized in FPGA 15

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