Introducing and starting development on the iCE40 FPGA from Lattice Semiconductor

Published on November 18, 2016

Introducing and starting development on the iCE40 FPGA from Lattice Semiconductor

Hello! Today we will get acquainted with the new family of cheap and low-power FPGAs from the Lattice Semiconductor iCE40LP / HX / LM families, learn how to work with the proprietary iCEcube2 compiler and Sublime Text 3 code editor, and also program the chip on the Lattice iCEstick debug board using firmware written in SystemVerilog.

Everything will be accompanied by detailed instructions and screenshots.

It happens that microcontrollers are not suitable for some tasks in the development of iron, especially those related to high parallelism of data processing, the speed of their processing or other specific tasks, and something powerful from Cortex-A is seen as a sparrow cannon. Then, as a rule, the developer pays attention to FPGAs, providing him with a relatively low price full freedom of action at the lowest level of digital systems - individual logic elements and triggers. This allows you to make "your own chip" inside the FPGA, using its findings and the peripherals already built inside. For example, if you suddenly needed 50 timers with PWM, or ultra-fast data processing, or, say, SPI with 3 lines MISO and 2 MOSI, transfer 5 Gbps with 2 diff. lines - all this is quite feasible on the FPGA.

Among FPGA manufacturers, two have already gained popularity among developers - these are Altera and Xilinx, producing both the simplest FPGAs (MAX II, MAX 10, Spartan II, Spartan III), on which you can build logic of almost any complexity, and ultra-fast (Stratix 10, Arria 10, Spartan 7, Artix 7), capable of transmitting data at speeds up to 56 Gb / s, so that you have fast Internet. However, such nightmare speeds are not always needed.

Some features of the iCE40 FPGA family (data from the manufacturer’s website):

• HX series - high-performance FPGAs, LP - low power and LM - low power with built-in peripherals;
• From 384 to 7680 LUT cells;
• Low power consumption starting from 25 µW for some chips;
• Integrated in hardware SPI and I2C interfaces that facilitate chip configuration;
• Ability to implement interfaces: Parallel RGB, 7: 1 LVDS, MIPI DPI / DBI, HiSPi, subLVDS, LVDS, Parallel LVCMOS;
• Up to 128 kbps of internal RAM;
• There is no internal Flash memory, so you will have to connect external memory to the built-in automatic SPI interface (suitable models can be found in the Diamond Programmer firmware);
• BGA cases with a step of 0.35-0.4 mm, with a minimum size of 1.40x1.48x0.45 mm with a step of 0.35 mm, there is also a TQFP-144 case with a step of 0.4 mm.

If Altera and Xilinx have convenient development environments with a lot of lessons on them, then the software from Lattice is a compiler with a shell over Synopsys Synplify, and it seemed inconvenient to write code there, so I decided to just load the ready-made sources there. Software for other series - Lattice Diamond is not suitable for the iCE40 series, so for editing the code I installed the well-known Sublime Text 3 editor and installed a plug-in on it to support the SystemVerilog language. You can write in other languages, iCEcube2 automatically recognizes the language by file extension.

Well, if you have a USB iCEstick debug board (clickable images from manufacturers' websites): You can buy this one instead (the pinout and settings of the firmware will differ!):
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So, the detailed steps of installing the software, creating and configuring the project and the firmware, test code, firmware and monitoring the results:

1. Register on the Lattice Semiconductor website and download iCEcube2 .

2. Click “Click here to request your license” on the same page. After that, you will need to enter your MAC address in the field.

3. A letter with a license file will come to the mail.

4. Install iCEcube2, copy the license file to its folder, and indicate the path to it by running iCEcube2.

5. Install the FPGA firmware - Lattice Diamond Programmer .

6. Install Sublime Text 3 and the package manager for it .

7.In Sublime Text 3, click Preferences → Package Control, in the list that appears, click “Package Control: Install Package”.

8. We introduce "SystemVerilog". Click on the first (and only) item in the list, wait until the plug-in is installed (see the line at the bottom of the editor).

9. Create an empty file and save it as top.sv where the source code for your FPGA firmware project will be.

10. In iCEcube2, click New project (or the yellow leaf at the top), a window will open where you need to fill in the parameters as in the screenshot, indicating the path to the project:


11. Click Next, a window for adding source files to the project will appear, look for our top.sv file, double-click on it and click Finish.

12. The project is created, on the left is its tree and the steps for synthesizing, placing and tracing connections between cells. The Design Files item is expanded, there are all the files included in the project. Now there is only top.sv:


13. We will write the standard code for the LED blinking (well, if you have an iCEStick board):


14. Save the changes to the file and go to iCEcube2. Click on this file there twice, and when asked whether to update the file, answer “Yes”.

15. In iCEcube2, click Tools> Run All and wait for the project to assemble.

16. Click on the button with 16 green circles, Package View:


17. The pin editor opens, in which you can correlate the inputs and outputs of your module on SystemVerilog and the outputs of the FPGA case. You can scale the body diagram (Ctrl + rotate the mouse wheel) and move it (by dragging the cursor):



18. If you download the datasheet for debugging iCEstick, you can find out that the clock generator is connected to 21 outputs, and 5 LEDs to 95 (green), 96, 97, 98 and 99 (red) findings. In the left pane of the Port, you need to open the led [4: 0] bus, which we started instead of one output so that on those diodes that we will not blink, there will be no iron 0, otherwise they will dimly light. Now use the mouse to drag and drop all the items led [0] .. led [4] to the pins to which the LEDs are connected, and clk to the 21 pins.

nineteen.If everything is done correctly, then these conclusions on the diagram will turn green. After that, right-click on each of them and click Lock in the drop-down menu, after which locks will appear on them. This will save you from pinout reset when recompiling the code. Now save the pinout by pressing Ctrl-S. In the following windows, click OK and Yes:



20. Again click on 16 circles (Package view). The resulting picture looks like this:



21. Click Tools → Run All and wait for the full compilation of the project

22. Insert the iCEstick debugging into the USB port of the PC and launch the Diamond Programmer, click File> New File there. A window will open in which you can click Detect Cable, or you can select these parameters manually:


23. Click OK and wait for the scan:


24. If everything is ok, a line will appear:



If everything is bad, try a different USB port.

25. We fill in the parameters:



26. In the Operation column, click on the inscription Fast programming, the window opens:


In which you need to select the SPI Flash Programming item in the Access Mode drop-down list, after which the window will increase, and now you need to fill in the remaining fields as in the screenshot:


27. Click OK, or Enter, whichever is more convenient, and then save the firmware configuration by pressing Ctrl-S.

28. Click Program and wait a minute until the FPGA is erased and programmed again:



29. We observe the result: the red LED blinks at a noticeable frequency:




Conclusion


We learned how to set up and assemble a project with a code in iCEcube2 software, configure the firmware and load the firmware into the FPGA chip. We wrote a test code for flashing the LED on the board and confirmed its performance.

In order to use the iCE40 family FPGAs in your projects, you need to study the datasheets for the selected chip and its debug boards. The cheapest chip in the family - ICE40UL640-SWG16ITR50 costs $ 1.53 per unit in Digi-Key, has 640 cells, 55 kB of RAM, and a WLCSP-16 body with a size of 1.4x1.48 mm. The most expensive chip in the series - ICE40HX8K-CT256 costs $ 12.78 per unit in Digi-Key, has 7,680 cells, 128 KB of RAM, and a 14x14 mm BGA-256 package.

In further articles, a review will be made of FPGAs similar in characteristics to other manufacturers and compared with iCE40 in price, speed, number of cells, variety of cases, availability in Russia, ease of use of the development environment, etc.