BCD decoder 7seg: synthesis and simulation

Synthesizing a BCD Decoder for a 7-Segment Display: From Truth Table to Simulation

A BCD decoder converts a 4-bit binary-coded decimal (0–9) input into signals for a 7-segment display. Each segment (a–g) is controlled by a logic function derived from the inputs x3 (MSB), x2, x1, and x0 (LSB). For digits 10–15 (1010–1111), all segments are turned off.

The truth table defines the segment states:

| Digit | x3 | x2 | x1 | x0 | a | b | c | d | e | f | g |

|-------|----|----|----|----|---|---|---|---|---|---|---|

| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |

| 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |

| 2 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |

| 3 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |

| 4 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |

| 5 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |

| 6 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |

| 7 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |

| 8 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |

| 9 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |

Logic Function Synthesis Methods

For each segment, a Boolean function is synthesized. The method is chosen based on whether ones or zeros dominate:

• SOP (Sum of Products, using ones): conjunctions of minterms with output 1, joined by disjunction. Best when >50% outputs are 1.
• POS (Product of Sums, using zeros): disjunctions of maxterms with output 0, joined by conjunction. Best when >50% outputs are 0.

Example for segment A (2 zeros: 1, 4) — POS:

• Row 0001: (x3 ∨ x2 ∨ x1 ∨ ¬x0)
• Row 0100: (x3 ∨ ¬x2 ∨ x1 ∨ x0)
• A = (x3 ∨ x2 ∨ x1 ∨ ¬x0) ∧ (x3 ∨ ¬x2 ∨ x1 ∨ x0)

Example for E (4 ones) — SOP:

• 0000: ¬x3 ∧ ¬x2 ∧ ¬x1 ∧ ¬x0
• 0010: ¬x3 ∧ ¬x2 ∧ x1 ∧ ¬x0
• 0110: ¬x3 ∧ x2 ∧ x1 ∧ ¬x0
• 1000: x3 ∧ ¬x2 ∧ ¬x1 ∧ ¬x0
• E = union via ∨.

Expression Minimization

Simplify using Karnaugh maps or online calculators. Final minimized expressions (sum of products):

• a: ((¬x0 ∧ ¬x2) ∨ x3 ∨ x1 ∨ (x0 ∧ x2))
• b: ((¬x0 ∧ ¬x1) ∨ ¬x2 ∨ x3 ∨ (x0 ∧ x1))
• c: x3 ∨ x2 ∨ ¬x1 ∨ x0
• d: ((¬x0 ∧ ¬x2) ∨ x3 ∨ (¬x0 ∧ x1) ∨ (x0 ∧ ¬x1 ∧ x2) ∨ (x1 ∧ ¬x2))
• e: ((¬x0 ∧ ¬x1 ∧ ¬x2) ∨ (¬x0 ∧ x1 ∧ ¬x3))
• f: ((¬x0 ∧ ¬x1) ∨ x3 ∨ (¬x0 ∧ x2) ∨ (¬x1 ∧ x2))
• g: ((¬x0 ∧ ¬x1 ∧ ¬x2) ∨ (¬x0 ∧ x1 ∧ ¬x2) ∨ (x0 ∧ x1 ∧ ¬x2) ∨ (x3 ∧ ¬x2 ∧ ¬x1))

These expressions are implemented using AND, OR, and NOT gates.

Hierarchical Implementation in Digital Deeds

Digital Deeds supports hierarchical blocks (.cbe for blocks, .pbs for schematics).

Step 1: Segment Block

• Create new block: 4 inputs (x3–x0), 1 output.
• Rename pins: double-click.
• Connect wires (Ctrl+W) according to formula, e.g., for A.

Step 2: Main Circuit

• New Circuit.
• Import Custom Components (7 blocks).
• Parallel inputs x0–x3 to all blocks.
• Outputs connected to the 7-segment display.

Testing: cycling through 0000–1001 displays correct digits. Simulator generates timing diagrams for debugging.

Key Takeaways

• Choose SOP or POS based on the density of 1s or 0s in the truth table.
• Minimization reduces component count: Karnaugh maps are optimal for 4 variables.
• Hierarchical blocks simplify scaling for FPGA/ASIC designs.
• BCD decoders are foundational for counters, timers, and digital displays.
• Simulation testing catches errors before physical prototyping.

— Editorial Team