NAND Flash Analytics

Over the years, LSI experts have come to understand the importance of analytics for interacting with NAND flash memory to optimize performance and increase its life span. In this regard, the company created a group that studies the behavior of NAND flash and describes the features of interaction with LSI controllers. I bring to your attention an interview with an expert in this field, Bill Hunt, chief engineer of the analytical department, which allows you to better understand what the group is doing.

Are all NAND flash the same?

Of course not. NAND flash specifications, performance and other characteristics vary not only from different manufacturers, they also differ between models of the same family. Often even the chips of the same model, produced at different times, vary, especially at the very first stages and subsequently. Sometimes, manufacturers specifically create different models of a single chip, addressed to different markets, for example, for corporations and custom solutions. Understanding the difference between NAND types is vital to building an effective solution.

What is the difference between NAND chips from different manufacturers?

There are two “levels” of difference between chip manufacturers: differences due to the difference in architecture, and differences between manufacturers using the same architecture. For NAND manufacturers with different designs and manufacturing processes, the differences are dramatic. They consist of different pinouts, power requirements, arrangement of blocks and pages, addressing schemes, commands, recovery procedures for reading failures, and much more.

Some manufacturers use similar designs and manufacturing processes. But even so, their products may have significant operational differences. Each device can have unique properties, depending on the settings during production, command, diagnostics. Even with standard interfaces such as ONFI and Toggle, there is no guarantee of the same operation. Each manufacturer has its own interpretation of these standards.

What are the differences between generations of NAND chips?

Reducing geometry in chip manufacturing requires a new architecture. The new architecture leads to changes in the operation and specifications of the NAND device. The biggest changes are caused by an increase in the density of memory chips. For example, the size and arrangement of blocks and pages must be changed to cope with the new architecture and increasing capacity. As memory cells become smaller and denser, error handling functions should also improve. The requirements for error correction codes (ECCs) and spare areas are growing. NANDs must also adapt to the increasing speed of bad blocks. The data transfer speed and performance of each new generation should also increase to meet user needs. This leads to changes in the interface timing specifications and the addition of new features. Generally,

What tests are done in the LSI flash analytics lab?



The flash analytics lab has two goals. First, we integrate NAND devices into SSDs with the LSI SandForce controller to make sure they work together. Second, we test NAND devices to see how flash memory works throughout its life cycle. We conduct testing in different operating modes. Understanding the behavior of NAND chips directly is crucial for developing solutions with the reliability and performance demanded by the market.



Are flash memory tests “outside” of their passport life cycle?

Yes. NAND providers do not always share the results and methods of their endurance tests, so we are forced to collect this data ourselves. Usually, we run write / erase cycles until the error level reaches a very large value or a fatal failure occurs. We also measure other parameters, such as backup volumes. Understanding the behavior of memory as it ages is simply necessary in order to predict how devices will behave in real-world scenarios.