May 25, 2009 at New Intel Xeon 5500 processor line (Nehalem)
At the beginning of this year, Intel introduced a new line of Xeon 5500 processors based on the Nehalem core. I met her at the Trinity Solutions seminar in Moscow on April 14th.
What is interesting about the new series, except for an increase in productivity and a reduction in energy consumption (without which nowhere)?
First of all, note that all processors of this line are multi-core (and only one of them is 2-core). Together with Hyper Threading technology, this gives up to 16 logical cores (as we know, some systems, for example, Win2k3, perceive single-core processors with HT as dual-core). In addition, Intel Turbo Boost technology allows you to dynamically change the frequency of each physical core separately to achieve the optimal performance / power ratio depending on the load.
But, if HT and ITB are not the latest and even not the most interesting developments, then QPI (QuickPath Interconnect) and IMC (Integrated Memory Controller) are new developments. If the second is more or less clear from the name (I’ll only get it, then the controller can work with DDR III in three-channel mode), then the first is (IMHO) the most interesting innovation.
What is a QPI? QPI is a high-speed bus for data exchange between processors (that is, a processor-to-processor connection) and a chipset (processor-to-chipset connections). The data transfer rate is 25.6 GB / s. At the same time, the bus can automatically correct connection errors (as one of the seminar participants noted, it can work, not work and pretend that it works). The main advantage of such a system is that if earlier, when there were any problems between the processors in the multiprocessor system, an inevitable conflict of equipment and BSOD occurred in the OS (or kernel panic in another OS :)), now when critical errors occur, QPI will be make attempts to fix them on the fly (a sign of this will be a decrease in productivity). The main task of the “processor-processor” connection is the exchange of data from random access memory (the memory controller integrated into the processor dictates the need to divide memory into groups according to the number of processors in the system) between processors. Connections "processor-chipset" allows processors to exchange data with PCI-devices, disk system and more.
Well, to top off a few links:
PS This is the first attempt to write habratopika. So I will be glad to all criticism.
What is interesting about the new series, except for an increase in productivity and a reduction in energy consumption (without which nowhere)?
First of all, note that all processors of this line are multi-core (and only one of them is 2-core). Together with Hyper Threading technology, this gives up to 16 logical cores (as we know, some systems, for example, Win2k3, perceive single-core processors with HT as dual-core). In addition, Intel Turbo Boost technology allows you to dynamically change the frequency of each physical core separately to achieve the optimal performance / power ratio depending on the load.
But, if HT and ITB are not the latest and even not the most interesting developments, then QPI (QuickPath Interconnect) and IMC (Integrated Memory Controller) are new developments. If the second is more or less clear from the name (I’ll only get it, then the controller can work with DDR III in three-channel mode), then the first is (IMHO) the most interesting innovation.
What is a QPI? QPI is a high-speed bus for data exchange between processors (that is, a processor-to-processor connection) and a chipset (processor-to-chipset connections). The data transfer rate is 25.6 GB / s. At the same time, the bus can automatically correct connection errors (as one of the seminar participants noted, it can work, not work and pretend that it works). The main advantage of such a system is that if earlier, when there were any problems between the processors in the multiprocessor system, an inevitable conflict of equipment and BSOD occurred in the OS (or kernel panic in another OS :)), now when critical errors occur, QPI will be make attempts to fix them on the fly (a sign of this will be a decrease in productivity). The main task of the “processor-processor” connection is the exchange of data from random access memory (the memory controller integrated into the processor dictates the need to divide memory into groups according to the number of processors in the system) between processors. Connections "processor-chipset" allows processors to exchange data with PCI-devices, disk system and more.
Well, to top off a few links:
- Page about Intel Xeon 5000 branch processors.
On it you can find a funny demo and product brief (English); - Trinity Solutions Company Event Page
Below are links to workshop materials.
PS This is the first attempt to write habratopika. So I will be glad to all criticism.