Intel Quartus Prime - everything you need to work with Intel FPGA

In 2015, Intel acquired Altera, one of the most famous developers of FPGA and SoC. Gradually, all Altera products - both hardware and software - changed their name, in particular, Altera Quartus design software for FPGA systems became known as Intel Quartus Prime . We often mentioned it in connection with the release of the next Intel FPGA, but we never described it in detail. Now there is time to do this, especially since several big releases have already been released since the name change, which brought new functionality and support for new devices.
So, Intel Quartus Prime contains everything you need to design systems based on Intel FPGA, SoC and Complex Programmable Logic Device (CPLD), starting from the very basics and further including debugging interaction, optimization, verification and modeling. There are currently three Quartus Prime delivery options:
- Intel Quartus Prime Pro Edition is designed to work with advanced latest generation FPGA and SoC options such as Intel Stratix 10, Intel Arria 10, Intel Cyclone 10 GX.
- The Intel Quartus Prime Standard Edition includes full support for previous generations of devices, as well as the Intel Cyclone 10 LP family.
- The Intel Quartus Prime Lite Edition is a tool for working with mass-segment families; it can be downloaded for free without additional licensing.
The compatibility matrix for version 18.1 is as follows.
| Devices | Pro | Standard | Lite |
|---|---|---|---|
| Stratix IV, V | ✓ | ||
| Intel Stratix 10 | ✓ | ||
| Arria ii | ✓ | ||
| Arria II, V | ✓ | ||
| Intel Arria 10 | ✓ | ✓ | |
| Cyclone IV, V | ✓ | ✓ | |
| Intel Cyclone 10 LP | ✓ | ✓ | |
| Intel Cyclone 10 GX | ✓ | ||
| Intel MAX series | ✓ | ✓ |
Now about the main functionality - again, with respect to various versions of Intel Quartus Prime. More information can be found on the product page .
| Functional | Pro | Standard | Lite |
|---|---|---|---|
| Design flow | |||
| Partial reconfiguration allows you to reconfigure part of the FPGA dynamically while the rest of the design continues to function | ✓ | ✓ | ✓ |
| Fast recompilation - if possible, the compiler will reuse the previous results of analysis and fitting and do not preprocess unchanged block designs | ✓ | ✓ | |
| Block Design - Incremental Block Compilation and Reuse of Block Design | ✓ | ||
| Incremental optimization - traditional fitting steps are subdivided into finer sub-steps for better flow control | ✓ | ||
| Design entry | |||
| Multiprocessing Support - Reduces Compilation Time | ✓ | ✓ | |
| A set of IP - intellectual property licenses for the most popular architectures and interfaces in FPGA | ✓ | ✓ | |
| Intel HLS Compiler - a high-level synthesis tool that accepts C ++ input and generates product-quality RTL code optimized for Intel FPGA | ✓ | ✓ | ✓ |
| Platform Designer - automatically generates interconnect logic for connecting IP functions and subsystems; in the Pro version has additional functionality | ✓ | ✓ | ✓ |
| Chip Scheduler - Demonstrates a visual representation of chip resources | ✓ | ✓ | ✓ |
| Interface Scheduler - Learn the architecture of device peripherals and efficiently distribute interfaces | ✓ | ||
| Logical blocking regions - a fitter directive to place certain elements or nodes within the same region | ✓ | ||
| Functional simulation | |||
| ModelSim-Intel FPGA edition software is a special version of ModelSim software for Intel FPGA that includes behavioral analysis, HDL tests, and TCL script execution | ✓ | ✓ | ✓ |
| Synthesis | |||
| Vhdl | ✓ | ✓ | ✓ |
| Verilog | ✓ | ✓ | ✓ |
| Systemverilog | ✓ | ✓ | ✓ |
| VHDL-2008 | ✓ | ||