Primitives for implementing 1-Wire master using PWM and ICP for STM8L and STM32
In a previous article , we presented an embodiment of primitives for asynchronous operation with a 1-wire bus for Atmel microcontrollers. Well, now your attention is invited to implement the same, but on more powerful microcontrollers of the STM8L family (for debugging, we used the usual STM8L-Discovery evaluation board with an removed LCD display). With minimal changes, the described implementation can be adapted for the STM32 family.
As a toolchain, IAR Embedded Workbench for STM8 was used with a free license (code size limit is 8Kb).
As the hardware driver for the 1-Wire bus, the circuit from the previous article was taken . The connection is as follows:
Do not forget to connect GND, power + 5V and power + 3V3.
Unlike the AVR, the STM8 (and STM32) family of microcontrollers offer a wider range of internal peripherals. Thus, the described project can be compiled in several ways:
In addition, due to the presence of PWM prohibition input timers (BREAK signal), it became possible to implement hardware-based protection against attempting to exchange data when active-pullup is turned on (i.e. to prevent 1-wire from being accidentally shorted to the ground when power is supplied to it to perform the transformations).
General Implementation Features
When primitives are not used, output signal PB1 maintains a low signal level (i.e., the modulating stage is not active). The timer is programmed in such a way that the duration of the period corresponds to the duration of the time slot plus the duration of the protective pause between bits (for the bit transfer procedure) or the total RESET pulse duration, the pause until the possible start of PRESENCE and the maximum duration of PRESENCE itself (for the RESET procedure).
The control registers PWM (TIMx_CCR1) and Capture (TIMx_CCR2) are programmed to use the shadow registers. This means that after the program change of the PWM register ((TIMx_CCR1), its value will only be used after the UEV signal appears inside the microcontroller. This signal is generated either automatically when the counter reaches the specified peak (period), or programmatically by setting the UG bit in the TIMx_EGR register) .
Immediately before starting PWM, the required pulse width of the least transmitted bit is calculated and loaded into the PWM register (TIMx_CCR1). After that, the timer is started by setting the CEN bit in the TIMx_CR1 register. At this point, the PWM signal is not yet active, because the MOE bit in the TIMn_BKR register was previously reset to 0. After that, the UG bit is set to TIMx_EGR programmatically, which activates the internal UEV signal, resets the current counter value to 0 and loads the contents of the PWM register (TIMx_CCR1) into its shadow copy used for comparison .
In addition, since the AOE bit was previously set in the TIMn_BKR register, the MOE bit in the TIMn_BKR register can be automatically set by the UEV signal, which will enable the PWM output. However, this will only happen if the BREAK signal is not generated, which is generated from the external active-pullup control (this is possible because the BREAK signal inside the microcontroller is generated directly by the signal value on the external pin, regardless of whether it is programmed for input or output mode) . Thus, if the active-pullup signal is active during the RESET procedure or when attempting to transmit / receive bit (s), the inclusion of the PWM output will be blocked.
The principle of operation of the IRQ-only implementation is the same as described in the previous articlewith the difference that instead of the up-down timer operation mode, the “up to the set value” counting mode is used. This became possible because the bits of the 16-bit timer are quite sufficient both for the formation of the time slot period for the transmission of one bit, and for the implementation of the procedure “generating a RESET signal with PRESENCE waiting”.
In this implementation, the calculation of the duration of the next pulse is performed during the processing of the interrupt that occurs when the transmission of the previous bit is completed.
Implementation using DMA with 8 and 16bit transmission is basically the same and differs only in bit depth for PWM and ICP. All pulse durations are calculated in advance before the timer starts. The pulse width of the least significant bit is loaded into the PWM register (TIMx_CCR1) as described above, and to load the remaining values, if necessary, the 1st DMA channel is programmed. All measurement results are always saved using the 2nd DMA channel.
The generated code is well within the limit of the free license from IAR, therefore, having an evaluation board on hand, you can immediately begin to experiment. And, thanks to the possibility of hardware debugging, you can also study the features of the functioning of the periphery of the microcontroller.
Note.
In the source code you can find a couple of high-level procedures for implementing the exchange protocol on the 1-Wire bus. They are quite working, but excluded from the project by conditional compilation directives. Look forward to using pthreads and the asynchronous implementation of the higher-level part of the protocol.
List of references:
As a toolchain, IAR Embedded Workbench for STM8 was used with a free license (code size limit is 8Kb).
As the hardware driver for the 1-Wire bus, the circuit from the previous article was taken . The connection is as follows:
- pin PB1 of the evaluation board is connected to the OCRA driver
- the PD0 pin of the evaluation board is connected to the ICP driver
- pin PA5 of the evaluation board is connected to the PULLUP driver
Do not forget to connect GND, power + 5V and power + 3V3.
Unlike the AVR, the STM8 (and STM32) family of microcontrollers offer a wider range of internal peripherals. Thus, the described project can be compiled in several ways:
- IRQ-only. The logic of work is implemented only by interrupts, without using DMA. This option compiles when the __DRV_ONEWIRE_DMA symbol is not defined.
Advantages of implementation:- Only 3 bytes of RAM required
- Ability to program a timer to any desired resolution
Cons of implementation:- A large number of interrupts (3 interrupts per transmitted bit)
- DMA with 8 bit transmission. Programming the timer and saving the results during the reception and transmission of bits is done using DMA. This option compiles when the symbol __DRV_ONEWIRE_DMA = 1.
Advantages of implementation:- 9 bytes of RAM required
- A small number of interrupts (one interrupt per 1st transmitted bit and 3 interrupts in case of successful completion of the exchange)
Cons of implementation:- Inability to program the timer for high resolution
- DMA with 16 bit transmission. Programming the timer and saving the results during reception and transmission of bits is done using DMA. This option is compiled when the symbol __DRV_ONEWIRE_DMA = 2.
Advantages of implementation:- A small number of interrupts (one interrupt per 1st transmitted bit and 3 interrupts in case of successful completion of the exchange)
- Ability to program a timer to any desired resolution
Cons of implementation:- Requires 17 bytes of RAM
In addition, due to the presence of PWM prohibition input timers (BREAK signal), it became possible to implement hardware-based protection against attempting to exchange data when active-pullup is turned on (i.e. to prevent 1-wire from being accidentally shorted to the ground when power is supplied to it to perform the transformations).
General Implementation Features
When primitives are not used, output signal PB1 maintains a low signal level (i.e., the modulating stage is not active). The timer is programmed in such a way that the duration of the period corresponds to the duration of the time slot plus the duration of the protective pause between bits (for the bit transfer procedure) or the total RESET pulse duration, the pause until the possible start of PRESENCE and the maximum duration of PRESENCE itself (for the RESET procedure).
The control registers PWM (TIMx_CCR1) and Capture (TIMx_CCR2) are programmed to use the shadow registers. This means that after the program change of the PWM register ((TIMx_CCR1), its value will only be used after the UEV signal appears inside the microcontroller. This signal is generated either automatically when the counter reaches the specified peak (period), or programmatically by setting the UG bit in the TIMx_EGR register) .
Immediately before starting PWM, the required pulse width of the least transmitted bit is calculated and loaded into the PWM register (TIMx_CCR1). After that, the timer is started by setting the CEN bit in the TIMx_CR1 register. At this point, the PWM signal is not yet active, because the MOE bit in the TIMn_BKR register was previously reset to 0. After that, the UG bit is set to TIMx_EGR programmatically, which activates the internal UEV signal, resets the current counter value to 0 and loads the contents of the PWM register (TIMx_CCR1) into its shadow copy used for comparison .
In addition, since the AOE bit was previously set in the TIMn_BKR register, the MOE bit in the TIMn_BKR register can be automatically set by the UEV signal, which will enable the PWM output. However, this will only happen if the BREAK signal is not generated, which is generated from the external active-pullup control (this is possible because the BREAK signal inside the microcontroller is generated directly by the signal value on the external pin, regardless of whether it is programmed for input or output mode) . Thus, if the active-pullup signal is active during the RESET procedure or when attempting to transmit / receive bit (s), the inclusion of the PWM output will be blocked.
The principle of operation of the IRQ-only implementation is the same as described in the previous articlewith the difference that instead of the up-down timer operation mode, the “up to the set value” counting mode is used. This became possible because the bits of the 16-bit timer are quite sufficient both for the formation of the time slot period for the transmission of one bit, and for the implementation of the procedure “generating a RESET signal with PRESENCE waiting”.
In this implementation, the calculation of the duration of the next pulse is performed during the processing of the interrupt that occurs when the transmission of the previous bit is completed.
Implementation using DMA with 8 and 16bit transmission is basically the same and differs only in bit depth for PWM and ICP. All pulse durations are calculated in advance before the timer starts. The pulse width of the least significant bit is loaded into the PWM register (TIMx_CCR1) as described above, and to load the remaining values, if necessary, the 1st DMA channel is programmed. All measurement results are always saved using the 2nd DMA channel.
The generated code is well within the limit of the free license from IAR, therefore, having an evaluation board on hand, you can immediately begin to experiment. And, thanks to the possibility of hardware debugging, you can also study the features of the functioning of the periphery of the microcontroller.
Note.
In the source code you can find a couple of high-level procedures for implementing the exchange protocol on the 1-Wire bus. They are quite working, but excluded from the project by conditional compilation directives. Look forward to using pthreads and the asynchronous implementation of the higher-level part of the protocol.
List of references: