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FPGA VGA card: Verilog and timings

https://sudonull.com/fpga-vga-card-verilog-and-timings

Create a VGA video card on Altera EP4CE15 FPGA following Ben Eater's lessons. Verilog modules, counters, 2-bit color. Code and timings 800x600@60Hz for middle/senior. Study the implementation.

GPT-5.4 Pro solved Erdős problem No. 1202 from Green's list

https://sudonull.com/gpt-5-4-pro-solved-erdo-s-problem-no-1202-from-green-s-list

Learn how GPT-5.4 Pro with Liam Price disproved Erdős's hypothesis in additive combinatorics. Counterexample with a linear proportion of surviving numbers. Details for mathematicians and AI developers.

SAP-1 Assembly in Turing Complete: guide

https://sudonull.com/sap-1-assembly-in-turing-complete-guide

Step-by-step assembly of SAP-1 computer in Turing Complete simulator. Microcode, ROM, commands. For middle/senior devs. Download files and assemble your own 8-bit CPU.

From other projects

Dresden Beats Bochum: Bobzien Masterclass Shifts Table

https://lrivo.com/dresden-beats-bochum-bobzien-masterclass-shifts-table

Dynamo Dresden secure a crucial win over Bochum thanks to Ben Bobzien's playmaking. See how the result impacts the 2. Bundesliga standings and what's next.

Rúben Neves Slams Referee Amid Al-Hilal Title Push

https://lrivo.com/ru-ben-neves-slams-referee-amid-al-hilal-title-push

Al-Hilal's Rúben Neves criticizes refereeing after a draw that impacts their Saudi Pro League title fight against Al-Nassr. Get the full story.

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