November 11, 2014 at 00:31Circuit> Board> FPGA
On Habré there are articles for beginning FPGAs, there are articles with reviews of means of trace of printed circuit boards. I already referred to some of them in my first article on the creation of printed circuit boards . In the second article about SimBank in the comments, I had a dialogue about the complexity of developing FPGAs and supporting projects with it. The view was expressed that it was easier to assemble several simple devices instead of one complex one. Sometimes it’s really easier. When it comes to two, four, eight devices. The series can be continued with the usual multiplicity. To overcome the threshold of comfort. Two is a bunch? And what if there are people who wish for 100 or 200 devices of the same type?
To use or not to use FPGAs in one or another task, everyone decides for himself (or with colleagues).
Today I want to bring to your attention an article about the features of creating a printed circuit board with FPGA. We take the IO Designer tool from Mentor Graphics as the basis.
Some may find the material useful, some simply interesting, and some may not agree with me.
For some CAD systems, such as Altium Designer, updates are periodically released with the bases of new chips. (If you are a subscriber to updates). For Cadence and OrCAD, component manufacturers often lay out library symbols for circuit symbols and circuit board cells. For Mentor Graphics ExpeditionPCB, this luxury is more an exception than a rule. About PADS (another product for end-to-end design of printed circuit boards from Mentor Graphics) I will not say, I did not have to work with it. In the design system itself, a very convenient library component manager. To build the footprint of components for printed circuit boards in accordance with the requirements of the IPC-7351 standard, there is a very successful program “LP Wizzard”. (Land pattern wizzard). To create graphic schematic symbols of simple and not so components, it is possible to import from a file. And for FPGAs, there is "IO Designer", which combines the symbolic, circuit, paid (from the printed circuit board) and Verilog (VHDL) parts of the project.
IO Designer contains a knowledge base for most FPGAs and CPLDs from FPGA manufacturers such as Xilinx, Altera, Lattice, and Acctel. Along with the release of new families from FPGA manufacturers, MG is releasing updates to the FPGA databases. But the new documentation on the chip family will still have to be studied.
Suppose we chose FPGAs, studied (got acquainted) its features and are ready to create.
When creating a project, we can choose the manufacturer of the FPGA, the FPGA family, the type of case, and the number of elements. And also indicate the speed of the components (to set the exact Part Number).
For FPGAs, most of the contacts can be configured both for output and input. Connect at first glance - I do not want to. Here we bring the SD card controller, here RGMII for Ethernet PHY, etc. It was not there. With such a bold bypass of contacts for convenience, we can stumble upon a mass of pitfalls. Reading the documentation will avoid most of them, but it will not be easier to assign contacts from this. And the design of the board can turn into a mess.
Everything in this image is not so bad, because it was created “artificially” on the basis of a well-developed project. Usually the first time things are not so smooth. And at the stage of adding FPGAs, not all elements are still placed on the board. But it is specially noted that the signals from the lower left connector do not come to the lowest corner of the FPGA. As a result, they intersect with other signals and during tracing may require both additional vias and additional layers of the board. Which in the end will increase the cost of production.
The options for configuring contacts are also very limited. It’s good if our board is created for one specific product. There are conclusions of adjacent elements, we create response buses / signals for them in the FPGA. We launched a pilot project in CAD for FPGAs. If everything succeeds, then you can give it to the trace.
As a derogation: EMNIP on Xilinx Spartan-6 had specially assigned pins for DDR memory, which were then conveniently traced when the microcircuits were correctly placed on the board. And there was no need to move them then to interchange.
Often, according to the technical requirements, it is necessary to bring some kind of universality and our board will be used in the future for several projects. This is how we design a central board with a processor for working with many other devices, a kind of debugging board with an FPGA, a processor and an OS “for our own”. And here you need to provide a lot. Leave if you need one pin on the connector for synchronization, or for outputting a signal from the PLL. It will determine the directions of signals on the bus: input, output or bidirectional. If our central board is always a master, then such signals to the address bus or control can only be made to the output.
If we have a response on the bus from a slave board like WAIT or BUSY, then on the master board you can assign them to pins that can only be inputs. You can also do with conclusions determining the presence of the board.
Such a purpose, at first glance, limits the possibilities for subsequent tracing and shuffling of signals. But as practice shows, it is better to know such restrictions in advance. And not just assign “Inout” to all signals.
We can choose a file from where to get a list of signals. This can be a test project, a file on Verilog or VHDL.
If a test project has not yet been done, then we may not specify such a file. And then just create signals in the program window. Types of signals by default. For single signals and for differential.
Next, we can designate a place where we will later upload the file with our contact location.
Then you need to decide how we want to work with the circuit, whether we need full-fledged symbols or just creating circuits in the circuit design, and the descriptions of all contacts will be transmitted only in the form of an exchange file with CAD FPGA.
I always liked the option when you do not need to create circuit elements, and all exchanges go through internal unknown paths. But, working in a team, you have to accept more mundane rules of the game. So, according to the corporate standard for designing circuits, I always needed to divide the symbol into banks, to take out separately configuration circuits, land, power, and others. There are pros in this division, but there are also disadvantages. I had to do a schematic symbol. For FPGAs with 484 contacts, it is not so difficult to correctly make a circuit symbol, as it might seem to someone. But for a chip with 1172 contacts, this occupation is very tiring. Most contact names have long and similar names and are easily confused. You can generate all the characters automatically. But then they do not coincide with "corporate" preferences. In IOD, you can easily create a symbol from a database of elements by simply dragging it from the contact list window to the symbol window. I can’t say that it’s as easy as playing Farm Frenzy, but at this point we can simply assign signals to the contacts of the chip with the mouse. In this case, you can specify how to designate by name, by function, by contact number or in your own way. I usually choose the display for the functional purpose. Since in my opinion such a name is more informative and then the diagram shows what kind of signal you can get here. according to functionality, by contact number or in your own way. I usually choose the display for the functional purpose. Since in my opinion such a name is more informative and then the diagram shows what kind of signal you can get here. according to functionality, by contact number or in your own way. I usually choose the display for the functional purpose. Since in my opinion such a name is more informative and then the diagram shows what kind of signal you can get here.
From observations, I can note that the last names in Xilinx (for families of the 6th and 7th series) are rather meek and informative.
IO_L6N_T0_VREF_13
IO - I / O
contact L6N - designation of a differential pair
T0 - designation of a byte inside which you can swap data signals for memory (this point needs to be clarified!)
VREF - here you can supply an external reference voltage if required by the standard of the selected signal for the bank and There is no way to connect it inside the FPGA.
13 - bank number.
Altera also sometimes comes across normal functional designations, but more often (my subjective opinion) are difficult to reproduce the names of contacts, which then do not fit on the sheet with the circuit. Perhaps if I were to make circuits with large amounts of memory, multipliers, or some kind of collider, then such a name would be useful to me.
IO_DIFFIO_T18p__DATA15_DQ3T0_X9__DQ3T9_X18_DQ5T27_X36
In this case, it helps to specify a Custom Label for the contact name. And enter the name you need with your hands. I usually copy the functionality and shorten it to
IO_T18p_DATA15_DQ
In this case,
IO - can be used for I / O
signals T18p - this is the number of the differential pair in the upper segment
DATA15- this contact can be used for parallel loading of the
DQ configuration - it says to me that this is a reduction from the functional purpose of the contact (there can also be DM and DQS)
This is one example of how to call a contact based on its functionality and for any specific project , in the first place some other sign will be displayed.
So, for example, at Altera, when using LVDS signals, an external load must be used. For some banks, this is a load resistor only on the receiving side, and for others it is also necessary at the output. This can be noted on the chart symbol in the Custom Label property. The same goes for PCI type signals. Not all banks can be assigned the 3.3V-PCI bus standard. And this can also be noted on the symbol. Despite the growing crowding out of it with the PCIe standard in desktop systems, it is still popular in industrial design. And some customers are looking for devices in this particular design.
You can add an inscription in the symbol for all contacts at once. This will reduce the amount of text inside the character. Since any additional information will overload the symbol and the circuit, a compromise is needed. I did this for Xilinx microcircuits, which have microcircuits compatible by contacts inside the same case with a different number of logic elements, but some of the contacts are not involved in “small” microcircuits. Then, part of the circuit was not soldered in the project and it was possible to install a more “light” microcircuit. Given this when distributing contacts, then you can save on missing components and the price of FPGAs.
For convenience, I make canned symbols. An exception can be made for configuration contacts. If the project has a complex synchronization structure, then you can collect CLK inputs into a separate symbol - local, global and others. Power contacts of VCCO banks are placed on the symbol together with the bank or on a separate one - at the request of the MAIN developer.
The power supply contacts of the core, VCCAUX, earth and other things, most often, I stand on separate characters.
Allegedly, now it is possible to create only a circuit on all the power contacts and not clutter up the circuit with a large number of contacts of the same type. This is not customary for us to do, so I am not familiar with such options. This can be found in the reference documentation or from webinars and training materials on the network on the site of Mentor Graphics and its representatives.
I transfer the created symbols directly to the circuit design, indicate the type of case, annotate the circuit and the microcircuit is attached to the circuit, circuit and IODesigner.
Creating and Assigning Signals
As described above, we can export signals from a file or create them ourselves.
You can assign signals both with the mouse and through import / export. By holding down the SHIFT, CTRL or ALT keys, you can reassign signals to already assigned contacts. Or assign all selected signals to one bank. Visually, banks are displayed in different colors. Contacts of different types are displayed with different icons. You can enable the display of differential pairs. Over time, busy signals will be shaded.
We update the circuit and see symbols already with signals on the circuit.
We look at how they connected on the board. Usually this is the porridge already shown above.
Sometimes I immediately make a simple list of signals so that they are automatically created in the system, then I drag them to other elements in the circuit editor.
There is an option to import a list of signals from the circuit.
By synchronizing the design of the circuit, board and IO Designer, we can call up the display of signals in the IO Designer window. With circuits running from the FPGA to the components connected to it.
Now we can comb our signals. Moreover, all this will be done automatically in accordance with the rules introduced by us. Configuration signals will not go anywhere. We can also pre-lock signals to prevent a change in their location.
Please note that the DRAM3_RESET_B signal, which must be assigned the LVCMOS_1.35V I / O standard and cannot be in the same bank as the SSTL signals of the standard, is assigned to bank 17, and all other DRAM3 * signals to bank 12. Since the system just four signals with LVCMOS_1.35V, they are assigned the standard LVCMOS1.8V and a level converter is installed.
Despite the apparent confusion of the signals, they are now straightened out in accordance with the assigned rules. For the convenience of working with a project in Quartus.
The image shows the separated components, and the lines extending to them from the FPGA. Sometimes, if not all the components are arranged, it is not possible to decompose all contacts on the first try for trouble-free tracing. Although it all depends on the task.
After such a distribution of contacts, you can already give the circuit to the final trace or trace it yourself.
You can also export to Verilog / VHDL file. We can export to * .ucf, * .pin or another file. Give it to the FPGA designer for a pilot project, suddenly something was not taken into account. But in a small team it is not always possible to immediately do this in view of the heavy workload of other projects. (Old improvements, new wishes of customers or parallel projects).
Limitations
This method has limitations that I do not always know how to get around. But basically they are connected with the need to do a lot of things for versatility and in reserve. We have to invent crutches and stuff. So, by default, Altera cannot place a differential signal next to a differential signal. The compiler will give a warning. We can get around it by setting the parameter SLEW_RATE = 0 MHz in Pin Planner Quartus. Then the compilation will complete successfully. Even if in fact, our signal will hang at a frequency of 20 MHz. There is no such parameter in IODesigner. As a result, in the circuit, these contacts are used last or I set the signal type so that it does not cause a conflict, for example, a PCB signal or a configuration signal.
There are other restrictions that are usually bypassed. But in general, I have a positive attitude towards them, since they make me look again at the documentation for the chip much earlier than the finished board arrives.
For those working in other design systems, some things may not seem obvious and may not be necessary. So, as far as I know (heard), Altium allows you to configure the compilation of the project for FPGA directly in the project with the circuit and the board. I am not aware of all its possibilities. And for the people who design it, you don’t need import into Quartus or ISE. But we have one person designing a circuit board, other people designing FPGAs. When I give the circuit for tracing, I try to describe the signals as correctly as possible, while giving the PCB designer some freedom of action to change the contacts. We agree on any warnings that arise as they accumulate.
In the end, I would like to say that “IO Designer” is not a panacea. It does not turn the design of a circuit, board, and FPGA project into an interactive game and does not exempt from studying documentation for microcircuits. But working with such a tool is much nicer. The article does not describe all of its advantages. Also, I can’t judge the completeness of the libraries for all microcircuits, since I only had to work with some of the Altera and Xilinx families. I somehow managed to work a little bit with C Lattice on the debugging kit, but it didn’t get to the circuit, and even more so to the board. I did not work with Actel at all. From the comments on Xilinx, I can note that in my version there is no direct transfer of the restrictions file to / from Vivado. Maybe it will come out with updates. But since I am not leading the Xilinx FPGA project, I did not understand what exactly the problem was. We managed to export via * .csv file.
This publication does not pretend to be a tutorial on “IODesigner”, there are many lessons from Mentor Graphics for this. I know that Megratek company conducts training in Russian. www.megratec.ru .
Also, as far as I know, Mentor Graphics is preparing to launch xPedition - a new version of the design system. What will be added specifically by IODesigner? Time will tell. Of those presentations that I saw, I was impressed with updating 3D displays in boards and designing devices with several boards in one project.
Also, in addition to the CAD systems that I called, there are others for printed circuit boards. Each one has a list of advantages and a list of “what is missing in Y as in X”. And if I did not name their advantages in comparison with the option of working through IOD - do not be offended. You can write about this in the comments. Or an article about how you design FPGAs in your CAD system.
To use or not to use FPGAs in one or another task, everyone decides for himself (or with colleagues).
Today I want to bring to your attention an article about the features of creating a printed circuit board with FPGA. We take the IO Designer tool from Mentor Graphics as the basis.
Some may find the material useful, some simply interesting, and some may not agree with me.
For some CAD systems, such as Altium Designer, updates are periodically released with the bases of new chips. (If you are a subscriber to updates). For Cadence and OrCAD, component manufacturers often lay out library symbols for circuit symbols and circuit board cells. For Mentor Graphics ExpeditionPCB, this luxury is more an exception than a rule. About PADS (another product for end-to-end design of printed circuit boards from Mentor Graphics) I will not say, I did not have to work with it. In the design system itself, a very convenient library component manager. To build the footprint of components for printed circuit boards in accordance with the requirements of the IPC-7351 standard, there is a very successful program “LP Wizzard”. (Land pattern wizzard). To create graphic schematic symbols of simple and not so components, it is possible to import from a file. And for FPGAs, there is "IO Designer", which combines the symbolic, circuit, paid (from the printed circuit board) and Verilog (VHDL) parts of the project.
IO Designer contains a knowledge base for most FPGAs and CPLDs from FPGA manufacturers such as Xilinx, Altera, Lattice, and Acctel. Along with the release of new families from FPGA manufacturers, MG is releasing updates to the FPGA databases. But the new documentation on the chip family will still have to be studied.
Suppose we chose FPGAs, studied (got acquainted) its features and are ready to create.
When creating a project, we can choose the manufacturer of the FPGA, the FPGA family, the type of case, and the number of elements. And also indicate the speed of the components (to set the exact Part Number).
For FPGAs, most of the contacts can be configured both for output and input. Connect at first glance - I do not want to. Here we bring the SD card controller, here RGMII for Ethernet PHY, etc. It was not there. With such a bold bypass of contacts for convenience, we can stumble upon a mass of pitfalls. Reading the documentation will avoid most of them, but it will not be easier to assign contacts from this. And the design of the board can turn into a mess.
Everything in this image is not so bad, because it was created “artificially” on the basis of a well-developed project. Usually the first time things are not so smooth. And at the stage of adding FPGAs, not all elements are still placed on the board. But it is specially noted that the signals from the lower left connector do not come to the lowest corner of the FPGA. As a result, they intersect with other signals and during tracing may require both additional vias and additional layers of the board. Which in the end will increase the cost of production.
The options for configuring contacts are also very limited. It’s good if our board is created for one specific product. There are conclusions of adjacent elements, we create response buses / signals for them in the FPGA. We launched a pilot project in CAD for FPGAs. If everything succeeds, then you can give it to the trace.
As a derogation: EMNIP on Xilinx Spartan-6 had specially assigned pins for DDR memory, which were then conveniently traced when the microcircuits were correctly placed on the board. And there was no need to move them then to interchange.
Often, according to the technical requirements, it is necessary to bring some kind of universality and our board will be used in the future for several projects. This is how we design a central board with a processor for working with many other devices, a kind of debugging board with an FPGA, a processor and an OS “for our own”. And here you need to provide a lot. Leave if you need one pin on the connector for synchronization, or for outputting a signal from the PLL. It will determine the directions of signals on the bus: input, output or bidirectional. If our central board is always a master, then such signals to the address bus or control can only be made to the output.
If we have a response on the bus from a slave board like WAIT or BUSY, then on the master board you can assign them to pins that can only be inputs. You can also do with conclusions determining the presence of the board.
Such a purpose, at first glance, limits the possibilities for subsequent tracing and shuffling of signals. But as practice shows, it is better to know such restrictions in advance. And not just assign “Inout” to all signals.
We can choose a file from where to get a list of signals. This can be a test project, a file on Verilog or VHDL.
If a test project has not yet been done, then we may not specify such a file. And then just create signals in the program window. Types of signals by default. For single signals and for differential.
Next, we can designate a place where we will later upload the file with our contact location.
Then you need to decide how we want to work with the circuit, whether we need full-fledged symbols or just creating circuits in the circuit design, and the descriptions of all contacts will be transmitted only in the form of an exchange file with CAD FPGA.
I always liked the option when you do not need to create circuit elements, and all exchanges go through internal unknown paths. But, working in a team, you have to accept more mundane rules of the game. So, according to the corporate standard for designing circuits, I always needed to divide the symbol into banks, to take out separately configuration circuits, land, power, and others. There are pros in this division, but there are also disadvantages. I had to do a schematic symbol. For FPGAs with 484 contacts, it is not so difficult to correctly make a circuit symbol, as it might seem to someone. But for a chip with 1172 contacts, this occupation is very tiring. Most contact names have long and similar names and are easily confused. You can generate all the characters automatically. But then they do not coincide with "corporate" preferences. In IOD, you can easily create a symbol from a database of elements by simply dragging it from the contact list window to the symbol window. I can’t say that it’s as easy as playing Farm Frenzy, but at this point we can simply assign signals to the contacts of the chip with the mouse. In this case, you can specify how to designate by name, by function, by contact number or in your own way. I usually choose the display for the functional purpose. Since in my opinion such a name is more informative and then the diagram shows what kind of signal you can get here. according to functionality, by contact number or in your own way. I usually choose the display for the functional purpose. Since in my opinion such a name is more informative and then the diagram shows what kind of signal you can get here. according to functionality, by contact number or in your own way. I usually choose the display for the functional purpose. Since in my opinion such a name is more informative and then the diagram shows what kind of signal you can get here.
From observations, I can note that the last names in Xilinx (for families of the 6th and 7th series) are rather meek and informative.
IO_L6N_T0_VREF_13
IO - I / O
contact L6N - designation of a differential pair
T0 - designation of a byte inside which you can swap data signals for memory (this point needs to be clarified!)
VREF - here you can supply an external reference voltage if required by the standard of the selected signal for the bank and There is no way to connect it inside the FPGA.
13 - bank number.
Altera also sometimes comes across normal functional designations, but more often (my subjective opinion) are difficult to reproduce the names of contacts, which then do not fit on the sheet with the circuit. Perhaps if I were to make circuits with large amounts of memory, multipliers, or some kind of collider, then such a name would be useful to me.
IO_DIFFIO_T18p__DATA15_DQ3T0_X9__DQ3T9_X18_DQ5T27_X36
In this case, it helps to specify a Custom Label for the contact name. And enter the name you need with your hands. I usually copy the functionality and shorten it to
IO_T18p_DATA15_DQ
In this case,
IO - can be used for I / O
signals T18p - this is the number of the differential pair in the upper segment
DATA15- this contact can be used for parallel loading of the
DQ configuration - it says to me that this is a reduction from the functional purpose of the contact (there can also be DM and DQS)
This is one example of how to call a contact based on its functionality and for any specific project , in the first place some other sign will be displayed.
So, for example, at Altera, when using LVDS signals, an external load must be used. For some banks, this is a load resistor only on the receiving side, and for others it is also necessary at the output. This can be noted on the chart symbol in the Custom Label property. The same goes for PCI type signals. Not all banks can be assigned the 3.3V-PCI bus standard. And this can also be noted on the symbol. Despite the growing crowding out of it with the PCIe standard in desktop systems, it is still popular in industrial design. And some customers are looking for devices in this particular design.
You can add an inscription in the symbol for all contacts at once. This will reduce the amount of text inside the character. Since any additional information will overload the symbol and the circuit, a compromise is needed. I did this for Xilinx microcircuits, which have microcircuits compatible by contacts inside the same case with a different number of logic elements, but some of the contacts are not involved in “small” microcircuits. Then, part of the circuit was not soldered in the project and it was possible to install a more “light” microcircuit. Given this when distributing contacts, then you can save on missing components and the price of FPGAs.
For convenience, I make canned symbols. An exception can be made for configuration contacts. If the project has a complex synchronization structure, then you can collect CLK inputs into a separate symbol - local, global and others. Power contacts of VCCO banks are placed on the symbol together with the bank or on a separate one - at the request of the MAIN developer.
The power supply contacts of the core, VCCAUX, earth and other things, most often, I stand on separate characters.
Allegedly, now it is possible to create only a circuit on all the power contacts and not clutter up the circuit with a large number of contacts of the same type. This is not customary for us to do, so I am not familiar with such options. This can be found in the reference documentation or from webinars and training materials on the network on the site of Mentor Graphics and its representatives.
I transfer the created symbols directly to the circuit design, indicate the type of case, annotate the circuit and the microcircuit is attached to the circuit, circuit and IODesigner.
Creating and Assigning Signals
As described above, we can export signals from a file or create them ourselves.
You can assign signals both with the mouse and through import / export. By holding down the SHIFT, CTRL or ALT keys, you can reassign signals to already assigned contacts. Or assign all selected signals to one bank. Visually, banks are displayed in different colors. Contacts of different types are displayed with different icons. You can enable the display of differential pairs. Over time, busy signals will be shaded.
We update the circuit and see symbols already with signals on the circuit.
We look at how they connected on the board. Usually this is the porridge already shown above.
Sometimes I immediately make a simple list of signals so that they are automatically created in the system, then I drag them to other elements in the circuit editor.
There is an option to import a list of signals from the circuit.
By synchronizing the design of the circuit, board and IO Designer, we can call up the display of signals in the IO Designer window. With circuits running from the FPGA to the components connected to it.
Now we can comb our signals. Moreover, all this will be done automatically in accordance with the rules introduced by us. Configuration signals will not go anywhere. We can also pre-lock signals to prevent a change in their location.
Please note that the DRAM3_RESET_B signal, which must be assigned the LVCMOS_1.35V I / O standard and cannot be in the same bank as the SSTL signals of the standard, is assigned to bank 17, and all other DRAM3 * signals to bank 12. Since the system just four signals with LVCMOS_1.35V, they are assigned the standard LVCMOS1.8V and a level converter is installed.
Despite the apparent confusion of the signals, they are now straightened out in accordance with the assigned rules. For the convenience of working with a project in Quartus.
The image shows the separated components, and the lines extending to them from the FPGA. Sometimes, if not all the components are arranged, it is not possible to decompose all contacts on the first try for trouble-free tracing. Although it all depends on the task.
After such a distribution of contacts, you can already give the circuit to the final trace or trace it yourself.
You can also export to Verilog / VHDL file. We can export to * .ucf, * .pin or another file. Give it to the FPGA designer for a pilot project, suddenly something was not taken into account. But in a small team it is not always possible to immediately do this in view of the heavy workload of other projects. (Old improvements, new wishes of customers or parallel projects).
Limitations
This method has limitations that I do not always know how to get around. But basically they are connected with the need to do a lot of things for versatility and in reserve. We have to invent crutches and stuff. So, by default, Altera cannot place a differential signal next to a differential signal. The compiler will give a warning. We can get around it by setting the parameter SLEW_RATE = 0 MHz in Pin Planner Quartus. Then the compilation will complete successfully. Even if in fact, our signal will hang at a frequency of 20 MHz. There is no such parameter in IODesigner. As a result, in the circuit, these contacts are used last or I set the signal type so that it does not cause a conflict, for example, a PCB signal or a configuration signal.
There are other restrictions that are usually bypassed. But in general, I have a positive attitude towards them, since they make me look again at the documentation for the chip much earlier than the finished board arrives.
For those working in other design systems, some things may not seem obvious and may not be necessary. So, as far as I know (heard), Altium allows you to configure the compilation of the project for FPGA directly in the project with the circuit and the board. I am not aware of all its possibilities. And for the people who design it, you don’t need import into Quartus or ISE. But we have one person designing a circuit board, other people designing FPGAs. When I give the circuit for tracing, I try to describe the signals as correctly as possible, while giving the PCB designer some freedom of action to change the contacts. We agree on any warnings that arise as they accumulate.
In the end, I would like to say that “IO Designer” is not a panacea. It does not turn the design of a circuit, board, and FPGA project into an interactive game and does not exempt from studying documentation for microcircuits. But working with such a tool is much nicer. The article does not describe all of its advantages. Also, I can’t judge the completeness of the libraries for all microcircuits, since I only had to work with some of the Altera and Xilinx families. I somehow managed to work a little bit with C Lattice on the debugging kit, but it didn’t get to the circuit, and even more so to the board. I did not work with Actel at all. From the comments on Xilinx, I can note that in my version there is no direct transfer of the restrictions file to / from Vivado. Maybe it will come out with updates. But since I am not leading the Xilinx FPGA project, I did not understand what exactly the problem was. We managed to export via * .csv file.
This publication does not pretend to be a tutorial on “IODesigner”, there are many lessons from Mentor Graphics for this. I know that Megratek company conducts training in Russian. www.megratec.ru .
Also, as far as I know, Mentor Graphics is preparing to launch xPedition - a new version of the design system. What will be added specifically by IODesigner? Time will tell. Of those presentations that I saw, I was impressed with updating 3D displays in boards and designing devices with several boards in one project.
Also, in addition to the CAD systems that I called, there are others for printed circuit boards. Each one has a list of advantages and a list of “what is missing in Y as in X”. And if I did not name their advantages in comparison with the option of working through IOD - do not be offended. You can write about this in the comments. Or an article about how you design FPGAs in your CAD system.