Trends in FPGA Design. Transfer
It is not the first year that the Wilson Research Group has conducted research on trends in FPGA and ASIC. According to the research, it is possible to determine the main vectors of development and changes that occur in the world of programmable logic.
On Habré, and even somewhere else not so often you can find information about the analytics of the development market for FPGA. It is not clear what and how it is changing, although it would seem that there are quite a few changes and interest in the market. People who are far from FPGAs have heard about the purchase of Altera by Intel.
So why is there no information? This post is designed to fix everything and bring order and clarity to the ranks of hardware vendors.He also tries to end the holivar between Verilog / SystemVerilog and VHDL supporters. Hurray!
And more ... here are the main points on FPGA, if you need ASIC - there are links to sources in the footer. If there is a big interest, you can write a separate post.
Most of the survey participants are electronics designers (hardware designer), verificarion engineers.
The study revealed a trend to increase the number of embedded processors in FPGA projects since 2014 (increased from 56% to 59%).
The increase is insignificant. And I understand why. Projects that use embedded processors add complexity to verification due to hardware and software interactions, as well as the need to implement complex interfaces.
The market for programmable SoC FPGAs such as Xilinx ZYNQ, Altera's Arria / Cydone (Intel) and Microsemi's SmartFusion is growing. The implementation of projects with an embedded processor has simplified noticeably, and now 36% of FPGA projects are being released on these chips.
At the same time, the share of projects using standardized on-chip interfaces instead of proprietary ones is growing. The growth of AMBA is due to the fact that in the above chips, as a rule, the embedded processor is ARM. And the standard is open.
48% of the time spent on the project is allotted for verification. This value is growing. For example, in 2014, 46% went for verification, and in 2012 - 43% of the project time.
If you look at the average time that verification engineers spend on performing various tasks related to a specific project, we will see that they spend most of their time finding and eliminating errors. As a rule, this time is significantly different from project to project.
The following data will help explain to the manager why you don’t take the project on time for so long :)
If you complete your project within a period of one and a half times the planned one, you will be far from the exception (approximately every tenth project surrenders that way).
During or before the deadline, only 35% of projects are surrendered.
As a rule, the backlog is due to the fact that 78% of the projects have “difficult” mistakes. At least 30% of projects have one error and the dependence of the number of projects on the number of errors is in the form of a Rayleigh distribution.
Types of errors in FPGA projects can be categorized from most popular to less. The most popular mistake that requires reworking of the project is a logical or functional error, then clocked errors, in analog-digital circuits, errors in the processor's proxy file, etc.
The main reasons for the appearance of errors in the logic and functionality of the project are:
1. Errors in the design, 2. Changes in the specification, 3. Incorrect or incomplete documentation, 4. Errors in their own or third-party IP blocks / testbenches and other elements of the project Assertion
tools, functional and code coverage, and by chance are increasingly used as testing tools - limited simulation:
47% of projects are adapted for assertion verification as a code verification strategy.
Languages that are used to design RTL .
There is a decrease in the number of VHDL code in projects. And this is a global trend. But this decrease is less relevant for European developers, where 79% of FPGA projects are written in VHDL, when the world average is 62%.
Languages used in tests
. SystemVerilog is the undoubted leader here. But here European developers are very different from the rest of the world. In Europe, VHDL for verification is used in 66% of cases, while SystemVerilog is used in 41%.
So VHDL is alive in some way. It is not clear, of course, why it is in Europe that statistics differs from the global one. Perhaps this is due to university studies. Although, on the other hand, I had to freelance and there were orders from American students, and almost all of them were on VHDL.
That's all.
I hope the article was useful to you.
Read more here. -
FPGA sources:
One
Two
Three.
ASIC sources:
One
Two
Three.
Priming
On Habré, and even somewhere else not so often you can find information about the analytics of the development market for FPGA. It is not clear what and how it is changing, although it would seem that there are quite a few changes and interest in the market. People who are far from FPGAs have heard about the purchase of Altera by Intel.
So why is there no information? This post is designed to fix everything and bring order and clarity to the ranks of hardware vendors.
And more ... here are the main points on FPGA, if you need ASIC - there are links to sources in the footer. If there is a big interest, you can write a separate post.
Let's start
Most of the survey participants are electronics designers (hardware designer), verificarion engineers.
The study revealed a trend to increase the number of embedded processors in FPGA projects since 2014 (increased from 56% to 59%).
The increase is insignificant. And I understand why. Projects that use embedded processors add complexity to verification due to hardware and software interactions, as well as the need to implement complex interfaces.
The market for programmable SoC FPGAs such as Xilinx ZYNQ, Altera's Arria / Cydone (Intel) and Microsemi's SmartFusion is growing. The implementation of projects with an embedded processor has simplified noticeably, and now 36% of FPGA projects are being released on these chips.
At the same time, the share of projects using standardized on-chip interfaces instead of proprietary ones is growing. The growth of AMBA is due to the fact that in the above chips, as a rule, the embedded processor is ARM. And the standard is open.
Now about verification
48% of the time spent on the project is allotted for verification. This value is growing. For example, in 2014, 46% went for verification, and in 2012 - 43% of the project time.
If you look at the average time that verification engineers spend on performing various tasks related to a specific project, we will see that they spend most of their time finding and eliminating errors. As a rule, this time is significantly different from project to project.
The following data will help explain to the manager why you don’t take the project on time for so long :)
If you complete your project within a period of one and a half times the planned one, you will be far from the exception (approximately every tenth project surrenders that way).
During or before the deadline, only 35% of projects are surrendered.
As a rule, the backlog is due to the fact that 78% of the projects have “difficult” mistakes. At least 30% of projects have one error and the dependence of the number of projects on the number of errors is in the form of a Rayleigh distribution.
Types of errors in FPGA projects can be categorized from most popular to less. The most popular mistake that requires reworking of the project is a logical or functional error, then clocked errors, in analog-digital circuits, errors in the processor's proxy file, etc.
The main reasons for the appearance of errors in the logic and functionality of the project are:
1. Errors in the design, 2. Changes in the specification, 3. Incorrect or incomplete documentation, 4. Errors in their own or third-party IP blocks / testbenches and other elements of the project Assertion
tools, functional and code coverage, and by chance are increasingly used as testing tools - limited simulation:
47% of projects are adapted for assertion verification as a code verification strategy.
HDL languages and not only
Languages that are used to design RTL .
There is a decrease in the number of VHDL code in projects. And this is a global trend. But this decrease is less relevant for European developers, where 79% of FPGA projects are written in VHDL, when the world average is 62%.
Languages used in tests
. SystemVerilog is the undoubted leader here. But here European developers are very different from the rest of the world. In Europe, VHDL for verification is used in 66% of cases, while SystemVerilog is used in 41%.
So VHDL is alive in some way. It is not clear, of course, why it is in Europe that statistics differs from the global one. Perhaps this is due to university studies. Although, on the other hand, I had to freelance and there were orders from American students, and almost all of them were on VHDL.
That's all.
I hope the article was useful to you.
Read more here. -
FPGA sources:
One
Two
Three.
ASIC sources:
One
Two
Three.