The future of the process or when Moore's law "dies"?

    Due to the fact that Moore’s law has been implemented for 50 years and the topic of how much “he has left” is discussed everywhere, including on Habr, I would like to share thoughts and plans of those who have to approve and support this law at least in the coming years.

    The following is my humble translation of the blog of people responsible for architecture and production at Intel: Mark Bohr and Sanjay Natarajan about how long, from their point of view, the process will be developed downward and which technology, from their point of view, will help maintain progress in this direction.

    Recently, the question often arises: "Is the process of reducing the size of transistors coming to an end?" Since no one believes that the process of improving technology can stop completely, a more reasonable version of this question will be: “Does it become technically or practically impossible to develop and introduce new technological processes approximately every two years, as predicted by Moore’s law almost 50 years ago?”
    Before answering this question, first look at the story. Once upon a time, the development of technologies for the semiconductor manufacturing process was much easier. The basic architecture of the MOS transistors was fixed, and the path to developing a new process was clear and simple: reduce the dimensions, reduce the vertical size, reduce the electric fields and - voila - a new faster and more energy-efficient transistor is ready. Of course, inventions such as point and halo (halo) implantations, silicide and nitride oxides for shutter were necessary to solve problems along this path, but the basic architecture remained the same for many generations. (When we talk about inventions, let's not forget about reducing the length of the interconnects, where copper conductors and planarization are proposed.)

    The end of scaling?
    Even during the heyday of these technologies, industry experts predicted the end of scaling. Experts say, “Optical lithography will reach its limits in the range of 0.75-0.50 microns,” “Minimum geometries [transistors] will be achieved in the range of 0.3 to 0.5 microns,” “X-ray lithography will be needed for sizes less than 1 micron,” “Copper interconnects will never work,” and “Scaling will end in about 10 years,” were made publicly, and everyone seems weird after a while.
    Perhaps the 130nm technology was the last real technology in this architecture. The early 1990s saw a huge change in the industry due to Intel's invention of uniaxial strained silicon in 90nm technology. This change is marked by the use of silicon-germanium alloys in the source / drain of the PMOS (p-channel MOS) transistor, it ushered in an era of great changes in materials in addition to existing geometric and electrical scaling. The 65nm stage was the last opportunity to use the industry's “workhorse”, SiON gate dielectric. Starting from 45nm, Intel made the transition to an exotic Hafnium dioxide-based dielectric with a high dielectric constant k and complex film sandwich structure. Finally, The 22-nm stage marked the end of the 50th year of the life of a planar MOS transistor and the transition to tri-gate technology of 3D transistors. The current state of technology resembles the transistor of the late 1980s about as much as a Ferrari resembles a horse-drawn carriage.

    Not only the structure of the transistor and materials has changed dramatically in recent decades, but the purpose of scaling the transistor has also changed. In the 1980s and 1990s, classic scaling provided significant improvements in transistor speed for microprocessors to operate at higher operating frequencies. But we paid the price for a very high power density with its increasingly high leaks. The 2000s ushered in an era when the power density limit and market demand for mobile computers changed the focus of transistor technologies from increased productivity to reduced power consumption. Modern computers, whether they are high-performance servers or low-power mobile phones, all require improved energy efficiency and reduced energy leakage.

    Radical new approaches
    The historical perspective is very important because it reminds us that the only constant in our industry is change (or, as Yogi Berra put it, “the future is not what it was”). In the future, a radically new architecture could create yet another colossal shift when gradual improvement stops working. There are many potentially attractive technology options like tunnel-type field effect transistors, BISFET (bilayer pseudospintronic field-effect transistors) transistors, graphene-based field effect transistors, and spin-based field effect transistors. All of them are actively researched in leading semiconductor companies.

    Another trend that is becoming increasingly important is the closer integration of technological processes, product design and architecture. Over the past few generations, limitations in the scaling process have led to design limitations, which in turn require closer joint optimization between the design and the process to achieve a better result. This trend is likely to continue and even grow. The future will include the integration of new processes, design and architecture, such as 3D packaging inside the chip, and not just inside TSV (through-silicon via) packaging and new approaches to computing, such as a process technology optimized for non-Boolean logic.

    It is possible that the new architecture of the process technology will make an equally powerful breakthrough tomorrow that “today's Ferrari” will look like an ancient “horse-drawn carriage”. Since we live and work in this amazing time for the semiconductor industry, and we hope to see another 50 years of the “work” of Moore’s law.

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