Hardware components of the onboard MPS of the unified strike fighter F-35

The priorities of modern military aviation are focused on high-quality situational awareness, so the modern fighter is a flying swarm of high-tech sensors. Information from these sensors is collected, processed and presented to the user by an on-board microprocessor system (MPS). Yesterday, HPEC hybrids (including CPU, GPU and FPGA) were used for its implementation. Today, for its implementation, single-chip SoC systems are used, which, in addition to assembling all the components on one chipset, also organize an intra-chip network (NoC) as an alternative to the traditional data transmission backbone. Tomorrow, when SoC systems become even more mature, the arrival of polymorphic nanoelectronics is expected, which will give a significant increase in productivity and reduce the rate of obsolescence.

Introduction

Whereas in the era of 4th generation fighters, the indicators of combat superiority were high speed and economical energy consumption, then in the era of 5th generation fighters combat superiority is measured, first of all, by the quality of situational awareness. [6] Therefore, a modern fighter is a flying swarm of all kinds of high-tech sensors, providing a total of "360-degree situational awareness." [5] The collection of information from these sensors, its processing and presentation, digestible for the pilot, require tremendous computing power.

All these calculations must be done on board, since the total intensity of the input data stream from the entire swarm of sensors (video cameras, radars, ultraviolet and infrared sensors, lidar, sonar, etc.) exceeds the bandwidth of external high-speed communication channels by at least 1000 times. [2] On-board signal processing is also attractive because it allows the pilot to receive relevant information in real time.

By “digestibility of presentation” it is meant that all information, no matter how heterogeneous, should be synthesized into a single “theatrical picture of hostilities,” [9] the interpretation of which should not turn into a puzzling analytical task (as it was in the old fighter models, where the pilot had to simultaneously monitor a dozen displays).

High performance integrated system

The responsibility for this theatrical production, or to put it more formally, the responsibility for solving this complex difficult task lies with the onboard MPS, which, in addition to high performance, should also provide a sufficiently low level of SWaP (size, weight and power consumption), which in itself is an “evergreen problem” ". [8] Today, a popular (but not the most advanced) solution in this regard is the use of three diverse processors located in one package: CPU, GPU and FPGA. The established name for such a hybrid is HPEC (High Performance Integrated System). [2] The key to it, a hybrid, of successful implementation is the thought-out architecture of the MPS, which takes the best characteristics from each processor, and bypasses their weaknesses. The goal of the HPEC architecture is to to achieve the synergy effect - when the performance of the final hybrid system significantly exceeds the total performance of its constituent parts. T.O. Hybrid architecture combines several different types of processors in one package. The idea is that if you use the strengths of each individual component, you can build an advanced HPEC system, which will result in stunning performance, and their baby will be a baby-SWaP. [10] Let us consider in more detail each of the three components of the HPEC architecture. that if you use the strengths of each individual component, you can build an advanced HPEC system, which will result in stunning performance, and their baby will be a baby-SWaP. [10] Let us consider in more detail each of the three components of the HPEC architecture. that if you use the strengths of each individual component, you can build an advanced HPEC system, which will result in stunning performance, and their baby will be a baby-SWaP. [10] Let us consider in more detail each of the three components of the HPEC architecture.

HPEC Hybrid Example

The advantage of FPGA is that algorithms are implemented on it in hardware, and such an implementation, as you know, is always faster. In addition, operating at relatively low clock speeds of the order of hundreds of MHz, FPGAs can perform tens of thousands of calculations per clock cycle and at the same time consume much less power than GPUs. FPGA is also difficult to compete in response time (hundreds of nanoseconds versus a dozen microseconds that the GPU can provide). It is also worth noting that modern FPGAs have the ability to dynamically reconfigure: they can be reprogrammed on the fly (without rebooting and stopping) - to adapt the algorithms to changing operating conditions. Therefore, FPGA (for example, Xilinx) is good for primary processing of data received from sensors. It sifts the raw information coming from the sensors and passes on a more compressed useful stream. FPGA is indispensable here, because a homogeneous data stream, the processing of which is also easy to parallelize, is exactly the task where FPGA is the leader of the genre.

FPGAs are currently the core of the most critical subsystems of the onboard MPS of military aviation: an on-board control computer, navigation system, cabin displays, brake systems, cabin temperature and pressure regulators, lighting devices, and aircraft engine control units. [14] FPGAs are also the core of on-board network communications, electro-optical guidance systems and other types of intensive resource-intensive computing for “integrated avionics modules” (IMA) aboard a “unified strike fighter” (JSF), such as the F-35. [five]

GPU (for example, Nvidia Tesla) - good for parallel processing of algorithms with intensive math and floating point. It does it better than FPGA and CPU. The massive parallel design of the GPU - consisting of several hundred cores - allows you to process parallel algorithms much faster than the CPU. FPGA is also good at parallel processing, of course, but not where floating-point operations are concerned. FPGA alone does not know how to do them, while the modern GPU provides a trillion floating-point operations per second - which, for example, is very useful for tasks such as stitching several gigapixel video streams.

A multi-core CPU (e.g. Intel Core i7) is good for cognitive processing.

So, taking the best characteristics of all processors and bypassing their weaknesses, you can achieve extraordinary computing power. In addition, other specialized processors can be included in HPEC to achieve even higher performance. For example, to solve the problems of an on-board navigation system, you can use PPU (Physics Processing Unit) - a hardware accelerator of physical calculations optimized for working with the dynamics of solids, liquids and soft bodies, for collision detection, for finite element analysis, for analysis of object faults and etc. [11] Other examples of specialized processors are a hardware accelerator for radar signal processing [1] and a hardware accelerator for graph analysis, [12] which will be indispensable for processing "big data". In foreseeable future,

Shrink MPS on one chipset

So, we examined the HPEC architecture, which is able to provide high performance with a sufficiently low level of SWaP. However, in this respect there is a more advanced solution: the SoC concept, the essence of which is to place the entire microprocessor system - on one chipset . SoC combines processor programmability with FPGA hardware configurability, providing an unrivaled level of system performance, flexibility, and scalability.

A significant shift in this regard towards the software component makes it possible to create multifunctional systems with ever-increasing capabilities and an ever-decreasing size and cost. The use of reprogrammable components also allows for cheaper and faster updates to legacy systems - without the need for hardware updates with every incremental improvement in their architecture, which is especially important for the military industry.

A typical SoC system includes:

• microcontroller, multi-core CPU, or DSP core;
• memory blocks, with a choice of: ROM, RAM, EEPROM and flash;
• timers, - including generators and phase locked loops;
• peripheral devices, including counter-timers, real-time timers, on and reset generators;
• external interfaces, including generally accepted ones: USB, FireWire, Ethernet, USART, and SPI;
• analog interfaces, including DAC and ADC blocks;
• voltage regulators and power management circuits;
• data transmission buses, through which all of the above blocks communicate;
• DMA controllers located between external interfaces and memory, which allow you to exchange data bypassing the processor core, thereby increasing the throughput of SoC.

A new trend in such a large-scale SoC integration, the last straw for the emergence of which was the growing popularity of eight-core processors, is the “intra-chip network” (NoC). This concept suggests abandoning traditional data transfer buses and replacing them with an intra-chip network . For example, Arteris Inc uses the NoC concept to manage intra-chip traffic and exchange control signals, resulting in a significant increase in throughput. [7]

SoC System Architecture by Arteris Inc

Conclusion

Summarizing the review of high-performance systems in general, and SoC in particular, as their most popular representative today, we can say that the evolution of the small form factor of embedded computing systems has taken place so quickly, and its impact on the architecture and capabilities of the system is so vast that it may take years for design engineers to integrate this cutting-edge single-chip concept into their solutions. In addition, since efforts to develop SoC systems are largely aimed at making hardware obsolete as slowly as possible, they tend to dominate reprogrammable components. Therefore, there is reason to believe that tomorrow's nanoelectronics will have the ability to fully customize, as a result, the line between hardware and software design will be completely erased. [7] In fact, such an event will mark the beginning of a new era - polymorphic nanoelectronics, which combines such conflicting characteristics as program-level flexibility and high-performance hardware acceleration. This will allow developers to take from their existing software and hardware architectures only their best characteristics, and their weaknesses are not something to ignore (as is done when designing an HPEC architecture), and in principle not be included in the final design of the device. At the same time, the probability of achieving the synergy effect (which was discussed in the discussion of the HPEC architecture) is significantly increased. Which will undoubtedly play a key role in improving the quality of situational awareness, which, as stated at the beginning of the article, today is the key to military superiority. Not only in airspace, but in the rest of the "theater of operations."