Elephant distribution: FPGA boards for educational projects with MIPSfpga

    A month ago, seminars on MIPSfpga ( 1 , 2 , 3 , 4 ) were held at Russian universities , and a gentleman from NIIIS named Anton Pavlov wrote a note about his own improvements MIPSfpga "MIPSfpga: outside the canon . " Since the professors welcomed the new product for teaching students of electronics in general, positively, the idea came up to help I start with boards, and at once for several people and organizations.

    In particular, in honor of the New Year, I am in cooperation with Vitaliy Kravchenko from univeda.ruWe are planning a small distribution of elephants, that is, free Terasic DE0-CV boards with FPGA Altera Cyclone V. So you can repeat the deed of Anton Pavlov. Since this particular distribution is done _not_ with Imagination Technologies money, not with Altera money and not with Elvis SPC money, but with the money of private benefactors, including me personally, the elephants will be distributed with rather specific conditions described below. The objectives of the event: 1. To increase the level of involvement of Russian universities in world research in the field of processor microarchitecture, design of SoCs and heterogeneous multi-core systems 2. To increase the number of Russian texts on MIPS Insider so that visitors from the international electronic industry and academia begin to understand that Russians are coming

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    3. To make, on behalf of the community, a bunch of training materials around MIPSfpga, which could be used by both teachers of Russian universities and university professors in other countries - the USA, Japan, China, etc.

    Conditions:

    1. It is desirable that the payee be a teacher, graduate student or student of a Russian university.

    2. It is desirable that this university was not Moscow State University, Moscow Institute of Physics and Technology, MEPhI, MIET and ITMO, which can receive these fees from other sources.

    3. It is very desirable that before receiving the board a creative friend would send me not only a description of the project, but also a code in Verilog or VHDL, C and / or assembler, with which he simulated a prototype of a future synthesized system in ModelSim or Icarus environment. Timing diagrams are also welcome.

    4. The project code upon completion is uploaded to http://github.com/MIPSfpga - see http://github.com/MIPSfpga/mipsfpga-plus

    5 as an example . It is also described in the Wiki section:

    5.1. What is in each file
    5.2. Hierarchy of hardware modules
    5.3. How to simulate - instructions with screenshots
    5.4. Simulation timing diagrams
    5.5. How to synthesize - instructions with screenshots
    5.6. Synthesis results - size and maximum frequency
    5.7. Description of the software part
    5.8. Photos of the working FPGA

    6. This is laid out on http://geektimes.ru in the form of article
    7. The same is laid out on http://silicon-russia.com
    8. The same is laid out at http://community.imgtec.com/forums/cat/mips-insider/mipsfpga
    9. Language (6), (7), (8) can be Russian or English

    10. If you don’t do a month with the board, it is withdrawn from you and transferred to someone else

    11. If we (UnivEDA and I) will do any events in Russia such as competitions or trainings, we will also take the board back for some time.

    Examples of projects with boards:

    1. Interface between MIPSfpga and sensors with interfaces SPI, I2C, UART and others. Sensors for humidity, temperature, sound, compasses, rangefinder, etc.

    2. The interface between MIPSfpga and external in relation to FPGA memory - SDRAM, DDR, etc. (in current examples, system memory is built from block memory inside FPGA)

    3. The interface between MIPSfpga and larger devices - VGA display, mouse, keyboard, joystick.

    4. Visualization of the cache by starting the processor at a frequency of 1 clock per second and outputting signals related to the transaction (request, miss, etc.).

    5. Visualization of the operation of the conveyor and arithmetic devices by starting the processor with a frequency of 1 clock per second and outputting control signals of the conveyor, etc.

    6. Adding commands to the processor using the CorExtend / User Defined Instructions (UDI) interface. An example is special encryption commands.

    7. Laboratory work with a demonstration of interrupt operation in different modes and an interrupt handler.

    8. Bridges between the AHB-Lite bus and other buses - AXI, APB, OCP, Wishbone, PLB, etc.

    9. Multiprocessor systems without coherence of first level caches and (for the most advanced) with coherent caches and implementation of protocols like MESI.

    10. Porting to MIPSfpga various programs and operating systems - from simple RTOS to various Linux variants (MIPSfpga supports TLB MMU).

    Please send suggestions to yuri.panchul@imgtec.com with a copy of yuri@panchul.com

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    Only registered users can participate in the survey. Please come in.

    Are you ready to do an educational or research project using MIPSfpga on the Terasic DE0-CV?

    • 0% Ready, and here is what I want to do (explain in the comments) 0
    • 14.8% Ready, but I need to think. I am inclined to projects of integration of the processor with external devices. 4
    • 11.1% Ready, but I need to think. I am inclined to projects exploring the insides of the processor. 3
    • 7.4% Ready, but I need to think. I am inclined to port projects to this board RTOS-s or my version of Linux 2
    • 7.4% I'm already having fun with other kernels - SPARC Leon for example 2
    • 0% I am quite entertained by simple kernels designed from scratch 0
    • 51.8% Not ready - I do not speak the languages ​​for describing the hardware, neither Verilog, nor VHDL 14
    • 11.1% Not ready - I do not know the concept of assembler and computer architecture 3
    • 22.2% Not ready - I do not understand how this board differs from Arduino 6

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