Porting MIPSfpga to Terasic DE0-CV with Altera Cyclone V FPGA

The other day, together with Alex and Vladimir (in the photo), we MIPSfpga (a package for introducing systems design on a chip) onto a Terasic DE0-CV board with Altera Cyclone V FPGA. This board is a pretty good solution for the educational Russian market, as it is cheap ($ 150) and it’s easy to buy on the website of the Taiwanese company Terasic, which delivers boards to Russia without unnecessary bureaucracy. We will try to use this at seminars at Moscow State University, MEPhI, MIET and ITMO (see the end of the post).



The porting process included creating a project in Altera Quartus II with the necessary parameters, cutting the size of the memory used inside the FPGA (in the future you just need to use the external memory - it is on the board), and selecting the right conclusions for connecting to the BusBlaster debug adapter board. BusBlaster is not used for debugging the hardware, but for loading into memory inside the system and debugging software running on the MIPS microAptiv UP processor core in the MIPSfpga system. (MIPS microAptiv UP is the same core that is inside the Microchip PIC32MZ microcontroller, but open source on Verilog)

To repeat this at home, you first need to cooperate with any university, since Imagination Technologies licenses MIPSfpga free of charge only to universities for educational and research purposes. An application for MIPSfpga can be made on the website of the educational programs Imagination Technologies:

community.imgtec.com/downloads/mipsfpga-getting-started-material-version-1-1

Next you need to get a BusBlaster debug adapter from Imagination Technologies or buy it on www. seeedstudio.com/depot/Bus-Blaster-V3c-for-MIPS-Kit-p-2258.html

Finally you need to have an account on GitHub and join the organization github.com/MIPSfpga , after which you can download the code from the github directory . com / MIPSfpga / boards / tree / master / de0_cv

Explanatory pictures about connecting the GPIO 1 pins of the Terasic DE0-CV board and the adapter for BusBlaster. The adapter was created initially for connection to the Basys3, Nexys4 and Nexys4 DDR boards from digilentinc.com. The

adapter had to be installed in the middle in order to avoid unwanted power and ground connections.

The adapter output that was originally intended for connection to Digilent boards : Connection label: Connection: Recommended connection of a BusBlaster sample with a Terasic DE0-CV FPGA board Recommended connection of a BusBlaster sample with a Terasic DE0-CV FPGA Recommended connection of a BusBlaster sample with a Terasic DE0-CV FPGA board















Now, in the Altera Terasic DE0-CV board, you can download / configure the MIPSfpga harver system, and load software programs for the MIPS microAptiv UP kernel inside the system into this system.

A description of what can be done with such a system is in a post about MIPSfpga seminars that will be held at Moscow State University, Moscow Engineering Physics Institute, Moscow Institute of Electronic Engineering, ITMO and Microchip Masters Russia this fall - see habrahabr.ru/post/265045 :

• Students can build their own prototypes of systems on a chip, combining a microprocessor core, memory and I / O devices designed by them
• Internal registers can be connected to the output ports and output information about the current state of the processor pipeline, caches and memory management devices. After that, the processor can be started at a low clock frequency and watch its work "in slow motion".
• Students can experiment with their cache options, design multi-core systems with specialized coprocessors, and experiment with dividing tasks into hardware and software.