# Processor Design (CPU Design) RAM Machine

• Tutorial

Part I
Part II
Part III
Part IV
Part V

An article on the RAM machine has already been published on Habré .
In general, an article about a RAM machine is on Wikipedia.

The RAM machine , which is mentioned in the book “Construction and Analysis of Computational Algorithms” - the authors: Aho, Hopkroft, Ulman - have a limited set of arithmetic commands (addition, subtraction, multiplication, division), an unconditional jump command, two conditional jump instructions. In our case, from the arithmetic commands there will be only addition and subtraction , the branch commands (transitions) will be identical to the commands given in the book.

The difference between LIttle Man Computer 'a (which I described in the previous parts of the cycle) and the RAM machine is a mechanism that provides indirect addressing (the ability to work with a number stored in memory as an address).

In order to work with the number stored in the memory as an address, connected to the address input of Memory Data multiplexer MUX , performs selection between actually location (coming from the instruction memory ) and the number representing the address and stored in the data memory .

We will load the number from memory into the register each time a new command is fetched from the Command Memory . When switching the multiplexer MUX , a transition occurs to the address recorded in the address register.

We will also load the load of the command address into the accumulator Acc as a number. To do this, we will increase the bit width of the address input of the multiplexer that selects the data to be loaded into the accumulator Ass . The address is loaded on the 4th input of the multiplexer.

The command will be processed in two cycles. To do this, connect to the clock generator two D-flip-flops that will switch each other when a clock signal arrives.

The first clock cycle loads the address into the address register, the second clock cycle loads the number into the accumulator Acc or into the data memory .

Connect 2 flags to the accumulator:

1. Acc flag = 0 . The flag is raised if the contents of the ass is zero.

2. Flag Acc> 0 . The flag is raised if the contents of the ass is greater than zero.

It turned out such a scheme, which can be downloaded from here.

The line going to allow the input of the battery, is needed to ensure that the scheme is not buggy.

Disable some commands and write a program that loads a zero cell of data memory.to the address stored in the zero cell. In the cycle, we will increase the value of the zero cell by one. So we will fill the data memory with sequence numbers.

1401 is loaded into Acc number 1
1100 add the number in Acc among a zero cell
2000 stores the result in zero cell
2080 load the number from the Acc address referenced by zero Box

write down program addernatural numbers.
We will write the natural numbers in the 1st cell, and their sum in the 0th cell.
To begin write program that loads the integers in the first cell
1401 is loaded into Acc number 1
1101 add the number in Acc to the number in the first cell
2001 stores the result in the first cell

in the cell will produce 0th summation. After increasing the number in the 1st cell, add this number to the 0th cell.
1300 we load into Acc a number from cell 0
1101 we add a number in Acc to the number in 1st cell
2000 we store the result in the 0th cell

Full text of the program
1401
1101
2001
1300
1101
2000
0010

In order to calculate members of an arithmetic progression, you must load the first item in the 0th cell , in the 1st cell to load the difference of arithmetic progression .
Next, you need to sum:
1300 is loaded into Acc number of cells 0
1101 add the number in the Acc to the number in the first cell
2000 stores the result in the 0th cell
Next, you need to jump on the 3 commands back and repeat this set of operationstime.

A classic RAM machine emulator (with separate read / write tapes) can be downloaded from here .

Let's check how the circuit consisting of two d-triggers works. This circuit provides two-clock mode.
We write the scheme of the usual d-trigger (without reset and enable). It will have two input ports - a data port and a clock port.
``````module dff
(
input  [1:0] key,
output  led
);
wire clk;
assign clk = key [0]; // тактовый вход
wire d =  key [1]; // вход данных
reg q;
always @(posedge clk)
q <= d;
assign led  = q;
endmodule
``````

The led LED indicates the status of the d-flip-flop.
We connect two dff in the general scheme.
The state of the first d-flip-flop will be indicated by the q1_led LED .
The state of the second d-flip-flop will be indicated by the q2_led LED .
Let's output a clock signal to a separate q3_led LED .

``````module dff_dff
(
input clk,
output q1_led, q2_led,q3_led
);
assign q3_led = clk;
wire d1_in;
assign d1_in=~q2_led;
dff dff1(
.clk(clk),
.d(d1_in),
.q(q1_led)
);
wire d2;
assign d2=q1_led;
dff dff2(
.clk(clk),
.d(d2),
.q(q2_led)
);
endmodule
``````

The RTL model of the dff_dff module looks like this

This scheme will not work on all boards, on some boards it is necessary to initialize d-triggers. For the same reason, such a scheme will not be simulated in ModelSim.