Building an HF SDR Receiver with STM32H723 and 16-bit ADC
The STM32H723ZGT6 enables the implementation of an HF SDR receiver covering the 1–30 MHz range using a Tayloe mixer. Audio output is provided via the internal 12-bit DAC or an I/Q stream to a PC over UAC1. The four-layer PCB measures 100×60 mm and features unused MCU pins brought out to PLS connectors for expansion.
The input circuit utilizes a Tayloe detector. Variants with transformers and balanced configurations were tested—no performance differences were observed. A simple design was chosen, despite a 1–2 dB sensitivity variation between the 160 m and 10 m bands.
Analog Path and Filtering
Signals from the mixer output are amplified by instrumentation operational amplifiers to suppress common-mode noise. The next stage is a 4th-order active low-pass filter using a Sallen-Key topology with cutoff frequencies of 48 kHz or 24 kHz.
The LPF frequency response shows sufficient attenuation at the band edges, but aliasing from strong signals at ±25–30 kHz is observed. For processing near zero frequency, this is acceptable.
Signals are fed to the 16-bit ADC inputs of the STM32H723ZGT6. The mixer is clocked by an Si5351 with a frequency multiplication factor of 4.
Software Implementation and Interface
The code is developed in STM32CubeIDE using HAL, TinyUSB for a composite USB device (COM + audio), and CMSIS-DSP for signal processing. Parameters are stored in external flash memory.
Control is via an encoder with a button and three function buttons. The display shows frequency, AGC/NOTCH status, S-meter, a ±24 kHz waterfall spectrum, and the demodulated bandwidth boundaries.
In USB mode with a PC, the spectrum is hidden, and status is displayed. The ADCs operate in dual independent channel mode (ADC1/ADC2) triggered by Timer 8 at 48 kHz. Dual mode caused signal mirroring and was not used.
- Post-digitization corrections:
- DC offset removal.
- Amplitude and phase calibration (coefficients per band).
I/Q data goes into a circular buffer: to PC—UAC1; standalone—FFT for waterfall, SSB/CW demodulation, AGC/NOTCH, DAC.
The DAC (12-bit) is clocked by the same Timer 8, buffered by OPAMP1 + RC low-pass filter. This is sufficient for amateur HF radio and broadcasting. An external PCM5102 (16–24 bit) was tested for improved quality.
Digital Signal Processing
DSP was explored through a C# application for analyzing I/Q from the ADC or WAV files, plus a test I/Q signal generator.
DSP code snippets are available on the author's website. Future plans include optimization and a transmitter section.
Key points:
- The 16-bit ADC in the STM32H723 handles real-time I/Q at 48 kHz.
- Tayloe mixer + Si5351 minimizes hardware costs.
- HAL + CMSIS-DSP accelerate development without performance loss.
- Standalone mode with onboard FFT, demodulation, and DAC.
- USB UAC1 for I/Q transfer to a PC without additional drivers.
— Editorial Team
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