Samsung introduced 3D-memory, Crossbar announced a breakthrough in RRAM

On Monday, representatives of Samsung Electronics announced the start of production of three-dimensional vertical NAND chips. In the new type of flash memory chips, due to the structure of silicon layers, better characteristics are achieved in comparison with two-dimensional chips; According to the statement of the Korean company, reliability will increase 2-10 times, and the performance of the recording process will double. Thus, Samsung became the first company in the world to launch the mass production of 3D NAND-memory chips.

The new technology will be used in a wide range of tasks, including the creation of solid-state drives with capacities from 128 gigabytes to 1 terabyte. The longitudinal recording density of the new microcircuits is 128 bits, and they are based on the technology of volumetric memory with a charge trap (3D Charge Trap Flash). The usual Charge Trap Flash was first introduced by Samsung back in 2006.

The number of vertical layers of microcircuits reaches 24, but their thickness is measured in nanometers, so even on a micrometer scale, the thickening will not be noticeable. Experts note that the limits of the number of layers are still unknown: today it is 24, in the next generation there will be 32, and then this number will increase.

The reasons for going into bulk layers are quite obvious: recently, flat scaling has become more and more complicated. With a decrease in the process technology of NAND flat chips, the number of electron leaks increases, which creates data errors that can only be corrected by adding new complicated error correction codes.

Volume chips use the old process technology of 40 and 50 nanometers. (For comparison: today, NAND-memory uses a technological process of the order of 20 nm.) This is due to the minimum thickness of the insulator between the layers, which also affects performance and reliability. And the performance of the presented 3D chips is still higher than that of a flat 10-nanometer NAND-memory.

The development of bulk chips took Samsung about 10 years, the company made more than 300 patent applications around the world. Representatives of the company are sure that the new technology opens the way to terabit chips of NAND-memory.

Currently, graphene-based microcircuits, phase-change memory, Racetrack memory, and resistive RAM are being considered as a replacement for NAND flash memory. The last type of memory is promised to be presented by the American startup Crossbar , according to the company , their RRAM chips will achieve a 20-fold superior in write speed over memory like NAND, and the power consumption will only make up part of the usual flash memory requests.



A company from the center of Silicon Valley - the city of Santa Clara - said that they managed to achieve a workable "simple and scalable" three-layer structure, so that using 3D technologies on one chip the size of a postage stamp (200 mm²) it will be possible to fit up to 1 terabyte information.

The promised superiority over today's limits of NAND-flash is great: a 20-fold reduction in power consumption, a 20-fold increase in recording speed, a 10-fold increase in durability while halving the chip size. Crossbar memory chips will have the easiest integration into chip-based systems.



Investors did not ignore a promising startup: Crossbar received $ 25 million from funds from Kleiner Perkins Caufield & Byers, Artiman Ventures and Northern Light Venture Capital. The fact that the company has already managed to create a working prototype at the production facilities of one of its partners helped this. Judging by at least three patents of the head of the company, Crossbar’s intentions are serious.

Like flash memory, RRAM is non-volatile, that is, the information on it will not be reset even if there is no power. According to company forecasts, the write speed will be 140 MB / s, read speed - 17 MB / s with a random reading delay of 30 nanoseconds. Three layers of chips consist of (from bottom to top) a non-metallic electrode at the bottom, a layer of amorphous silicon and a metal electrode.