IBM paves the way for flexible electronics

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At the International Electron Devices Meeting, held in San Francisco, IBM introduced a new and relatively inexpensive technology for manufacturing silicon electronics on a flexible plastic substrate.

On the one hand, IBM points to a slight decrease in the performance of transistors in the production process, but on the other, studies prove that a flexible and affordable technique can still be created with conventional processes at room temperature.

According to Davood Sharjerdi, an employee at IBM's TJ Watson Research Center, testing other one-dimensional and two-dimensional materials in flexible electronics encountered problems such as high contact resistance and poor gate isolation. In addition, other methods require either non-standard processes and materials, or require high temperatures in the manufacturing process.

IBM's controlled chipping or peeling approach was described earlier this year as a “kerfless” technique for removing silicon, germanium and III-V layers, which was used by IBM as evidence of the possibility of manufacturing low-power photovoltaic batteries .

This approach is, oddly enough, simple. The substrate with microcircuits is chipped and transferred to a flexible plastic tape. The result is a device with a shutter length of less than 30 nm and a shutter pitch of 100 nm.

According to experts from IBM, they were able to achieve the best performance for flexible SRAM-memory circuits with a voltage of VDD = 0.6V and a ring oscillator with a delay period of 16 ps with a power supply of 0.9V.

The process is as follows: it all starts with a substrate (very thin SOI-ETSOI), on which a nickel stress layer of about 5-6 microns thick is released. (ICs are manufactured using 22-nm CMOS technology using ETSOI plates with a diameter of 300 mm). A layer of elastic polyimide tape is applied over the stress layer. Then, at room temperature, scientists provoke a “stress rupture” from one edge of the substrate and propagate a “mechanically controlled” fault front over the entire surface of the substrate.

IBM uses ETSOI technology for two reasons. The first is the ultra-thin thickness of the substrates (60 angstroms), which allows you to scale the process below 30 nm and achieve a high density of circuit elements. The second - the presence of undoped transistor channels reduces the uneven distribution of impurities, which allows a significant spread in the voltage values ​​on the chip.

In order to improve mechanical flexibility, the researchers removed excess silicon under a buried oxide layer.



The second step to increase flexibility was to transfer the circuit to a plastic substrate, after which the “relatively thick” polyimide tape and nickel layer were removed. Polyimide is easy to disengage because it is bonded to the substrate by a heat-sensitive adhesive; nickel is removed by chemical etching.

IBM reported a slight decrease in the performance of circuits on flexible samples compared to the characteristics before transferring to flexible tape, and p-type transistors show a greater deterioration in parameters than n-type ones (30–40%).

To determine the cause of the deterioration, IBM monitored spalling on another ETSOI plate using the same processing steps. This time, the sample was rigidly fixed on a silicon wafer instead of being transferred onto a flexible plastic substrate. As a result, IBM scientists came to the conclusion that the decrease in the characteristics of p-type transistors was most likely caused by the mechanical action of the probe, and not by the stresses caused by the spallation process.

According to Dawood Scherardi, the yield of samples in the laboratory was 97%, and the problems they encountered were caused by the nickel deposition tool that affected this layer. He also added that the process is reproducible, and knowing the location of the stressor in the nickel layer, it is possible to determine the chipping depth with an accuracy of plus or minus 1 μm.

Via eetimes