FPGA Programmer

    I want to talk about how the http://marsohod.org project is developing .

    The goal of the project is to popularize design for FPGAs.
    The FPGA theme is gradually gaining popularity - and rightly so. After all, now we actually got a simple opportunity to create our own digital microcircuit. You do not need a nano-fab and a million dollars - you can just do everything with a computer and an FPGA chip on the developer's board. Do you know that 90% of chip manufacturers in the world do not have their own factories? They design and test in FPGAs, and order production to third-party manufacturers.

    Once upon a time, programming microcontrollers was considered almost a miracle. Now you can buy an Arduino shawl and teach a high school student to “blink an LED”.

    I want to show that FPGAs are also an affordable technology.

    The Mars rover board is the easiest and cheapest developer kit on the FPGA Alter EPM240T100C5 FPGA chip. The project - open source - the circuit board is on our website. In addition, more than 50 projects completed on the basis of our board have already been published .

    Next, I will talk about the programmer for FPGAs. It is believed that learning to design an FPGA is much more expensive than learning to microcontrollers. This opinion is partly due to the fact that FPGA vendor programmers are quite expensive.

    Now there is an alternative. You can make a simple USB programmer yourself!

    We have developed a very simple programmer on the FTDI FT2232HL chip. Here is one:

    This is a USB programmer with JTAG interface. Its scheme is also available on the site , which means you can make it yourself if you wish:

    The software that we ourselves wrote to it is SVF Player. Briefly tell you how it works.

    The Altera Quartus II FPGA design environment allows you to create files for programmers in different formats during the compilation of your project: POF, SOF, JAM, SVF. The Xilinx ISE design environment also allows you to create SVF files.

    Files in the SVF format is a simple text file with a description of the commands that need to be transferred to the FPGA chip through the JTAG interface for programming. An SVF (Serial Vector Format) file might look like this:
    !
    FREQUENCY 10000000.00 HZ;
    !
    TRST ABSENT;
    ENDDR IDLE;
    ENDIR IRPAUSE;
    STATE IDLE;
    SIR 10 TDI (2CC);
    RUNTEST IDLE 10003 TCK ENDSTATE IDLE;
    !
    !CHECKING SILICON ID
    !
    SIR 10 TDI (203);
    RUNTEST 53 TCK;
    SDR 13 TDI (0089);
    SIR 10 TDI (205);
    RUNTEST 53 TCK;
    SDR 16 TDI (FFFF) TDO (8232) MASK (FFFF);
    SDR 16 TDI (FFFF) TDO (2AA2);
    SDR 16 TDI (FFFF) TDO (4A82);
    SDR 16 TDI (FFFF) TDO (0C2C);
    SDR 16 TDI (FFFF) TDO (0000);
    !
    !BULK ERASE
    !
    SIR 10 TDI (203);
    RUNTEST 53 TCK;
    SDR 13 TDI (0011);
    SIR 10 TDI (2F2);

    The chip behind the JTAG interface has a so-called TAP controller that controls the testing and programming of FPGA chips. There are two registers in the TAP controller: the IR instruction register and the DR data register.

    The main commands in the SVF file are data transfer to the instruction register (SIR command) and transfer to the data register (SDR command).
    For example, the command SIR 10 TDI (203); says that you need to transfer a ten-bit number 0x203 to the IR register. Another example: SDR 16 TDI (FFFF) TDO (2AA2);says that you need to transfer the sixteen-bit number 0xFFFF to the DR register, but in response, the microcircuit must send the number 0x2aa2. Another important team is RUNTEST. It allows you to withstand pauses of a given duration during programming. Typically, pauses are maintained in the TAP states of the IDLE, IRPAUSE, or DRPAUSE controller.

    Correctly executing commands from the SVF file, you can “sew up” the FPGA chip. This is what our MBFDI SVF player program does.

    The JTAG chip programming and testing interface has only four main signals for data transfer: TCK - clock signal, TMS - transmission control signal, TDI signal - data transmitted to the chip and TDO - data read from the chip. To transfer data to the TAP registers of the IR and DR controller, you need to understand how to control the state of this controller. Let's try to figure this out.

    In fact, everything is quite simple. The states of the TAP controller are described by such a state machine: The

    TAP controller changes its state during the pulse of the TCK signal and depending on the value of the TMS signal.
    For example, it can be seen that in order to reset the TAP controller to the RESET state from any other state, it is enough to keep the TMS in the unit for at least 6 TCK pulses. If you want to switch from the RESET state to IDLE, you need to turn the TMS to zero and send at least one TCK pulse. From IDLE to the state of data transfer to the instruction register SHIFT_IR, these are just 4 TCK pulses when the TMS changes by 1-1-0-0.

    In our MBFTDI programmer, we use the FTDI FT2232HL chip in which all these JTAG lines are already managed. Our MBFTDI SVF player program reads an SVF file, interprets it, and sends commands to the FTDI chip controlling the JTAG lines. Description of JTAG FTDI chip commands is here .

    We have already tested our programmer with Altera MAX II, Cyclone II, Cyclone III, and some Xilinx chips.

    Of course, the programmer works on both Windows and Linux.
    Of course, the source code is available on our website in the download section or on GITHUB .

    I hope our project http://marsohod.org will help you quickly learn design for FPGAs.

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