# VHDL Delay Element

When designing various digital devices, in particular, controllers, it is required to organize a delay in the supply of the same signal to different outputs of the FPGA or to other elements inside the FPGA.

To begin, consider a similar situation with discrete logic. Usually, if a developer has a chip with six NOT gates (for example, 155LN1), he uses a serial connection of two elements as a delay element (10 ... 20 nanoseconds). Sometimes between them he inserts an RC circuit, with which you can make a delay time of 10 to 150 ns.

In the FPGA chip, a delay in this way cannot be arranged. It's all about the design synthesis features. The synthesis program perceives double negation as an unnecessary link (as an error) and eliminates it. On RC - circuits, it is also impossible to organize a delay, because the FPGA does not tolerate capacitive loading. Therefore, to organize the delay, I recommend the following method. It looks like a sketch:

The signal Ct is the same signal C, only delayed by 100 ns.

The reference time signal is a pulse signal with a certain frequency, which we need to use in the delay element. The period of this signal is the minimum possible time for which we can delay the signal Ct relative to C. In our case, the period of the reference time signal is 50 ns (frequency is 20 MHz).

Now I present to your attention the “iron” structure of the delay element:

In this structure there is only one incomprehensible element of blue color “?”. In fact, it is just a product of combinatorial logic. I will not decipher the structure of this element, I will only give its truth table:

Element T is an ordinary D-trigger with synchronization along the edge of signal C. Element ST is a counter of impulses of the reference frequency (time) REFTIME. In addition to the CLK clock input, it has a CE enable input. To generate a delay time of 100 ns, the counter must complete the count by counting to two (50 x 2 = 100). This parameter must subsequently be specified in the VHDL code of the counter. The pink element is 3-OR. Buffer BUF is needed to separate the output signal Ct and the internal signal CLR.

An experienced developer does not need to explain how this scheme works, but since beginners also read this article, I will give a brief description of the scheme.

An external REFTIME signal with a frequency of 20 MHz is supplied to the CT counter continuously. The input “D” of the trigger T is constantly tied to a logical unit. When a signal edge trigger C is applied to the input CLK, the first unit appears at the input of the 3-OR element. This element immediately allows the counter to count. As soon as the counter has counted to 2x, the D-flip flops to the logical zero state and logical zeros appear at its outputs together with the next REFTIME pulse. At the same time, an account is prohibited.

A feature of this scheme is that signal C is not only delayed by 100 ns, but also to the heap its duration is also shortened to 50 ns (i.e., to the period of the reference signal). In most cases, this feature is not critical and you just can not pay attention to it. But this feature can also be used purposefully to form the pulse duration.

I present to your attention the text of the VHDL program of the delay element: A

process with a label p1 describes the behavior of a D-trigger, while a process with a label p2 describes a behavior.