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AI in CERN Chips for LHC: Terabyte Filtering

https://sudonull.com/ai-in-cern-chips-for-lhc-terabyte-filtering

Learn how CERN integrates AI models into FPGA and ASIC for processing 40 EB of LHC data. Details on L1T/HLT triggers, HLS4ML, and HL-LHC plans. For developers.

SD card as ROM for RISC-V YRV FPGA

https://sudonull.com/sd-card-as-rom-for-risc-v-yrv-fpga

Implementation of SD card as program memory for YRV on Tang Nano 9K: FSM, SPI, tests with HELO. Instructions for FPGA developers. Study the code and optimizations.

Multithreaded RISC-V soft-processor for FPGA

https://sudonull.com/multithreaded-risc-v-soft-processor-for-fpga

Implementation of hardware multithreading in RISC-V soft-core: shadow registers, hart_table, CSR. Simplification of IRQ and context switching. Verilog sources for FPGA.

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