AI in CERN Chips for LHC: Terabyte Filtering

AI Models in CERN Chips: Real-Time Filtering of LHC Petabytes of Data

CERN engineers are integrating custom AI models directly into ASICs, FPGAs, and SoCs to process data streams from the Large Hadron Collider (LHC). Incoming speeds reach hundreds of terabytes per second, with the annual volume of raw data hitting 40,000 exabytes. A two-level AI trigger system filters out 99.98% of events in microseconds, keeping only relevant particle collisions.

In the 27 km ring, protons are accelerated to near-light speeds. Bunches collide every 25 ns, generating a billion events per second. Detectors capture megabytes per collision—without filtering, storage is impossible.

First Level: Level One Trigger on FPGA

Data is buffered in detectors for 4 µs using ASIC chips. Level One Trigger—a cluster of a thousand FPGAs—analyzes the stream over optical links at 10 TB/s.

The AXOL1TL AI-based algorithm makes decisions in 50 ns. It preserves 0.02% of events (110,000 per second), discarding the rest.

• Key L1T parameters:

- Input stream: 10 TB/s

- Analysis time: 50 ns

- Preserved events: 110,000/s

- Selection rate: 0.02%

AI integration into FPGAs is enabled by the HLS4ML compiler, which converts models into optimized C++ code for hardware acceleration.

Second Level: High Level Trigger with CPU and GPU

Selected events feed into the High Level Trigger (HLT). The system, with 25,600 CPU cores and 400 GPUs, reconstructs particle trajectories.

Output is 1,000 events/s, or about 1 PB of data per day. This data is distributed across 170 centers in 42 countries.

• HLT scale:

- CPU cores: 25,600

- GPUs: 400 accelerators

- Output: 1,000 events/s

- Daily volume: 1 PB

Standard AI frameworks can't meet the latency and volume demands, so CERN is building a custom stack: model compression, parallelization, and chip-specific optimizations.

Integrating AI into Hardware

HLS4ML is the key deployment tool. It generates Verilog/VHDL or C++ from TensorFlow/Keras models, minimizing latency.

Process:

• Train the model on a data subset.
• Quantization and pruning to shrink size.
• Compilation to RTL code for FPGA/ASIC.
• Testing on live streams.

This approach delivers predictable performance without software overhead.

High Luminosity LHC Upgrade

In 2026, the LHC will shut down for upgrades. The High Luminosity LHC (HL-LHC) will boost collision rates by 10x by 2031.

Trigger system evolution:

• L1T upgrade to 12.5 TB/s.
• New AI models for complex patterns.
• HLT scaling to exabyte levels.

This will enable detection of rare events like Higgs boson decays or dark matter signatures.

Key Takeaways

• CERN uses AI in chips to filter 40 EB/year of raw LHC data, preserving 0.0002% of events.
• Level One Trigger on FPGA with AXOL1TL analyzes 10 TB/s in 50 ns.
• HLS4ML compiles models to C++ for ASIC/FPGA, delivering microsecond latency.
• HL-LHC in 2031 will demand 10x trigger performance.
• The approach applies to edge computing in high-throughput systems.

— Editorial Team