At this stage of my training, I was encouraged by the availability of the Altera EP2C20F484C7 debug board (Cyclone-II family) at some stage of training.

FPGAs have capabilities that allow you to turn it into an integrated circuit with any digital logic function. Design is reduced to identifying programmable elements (jumpers or memory cells), after removing which only those connections that are necessary to perform the required functions remain in the circuit structure. In practice, this task is very difficult, since modern FPGAs contain on average several tens of thousands of jumpers. Therefore, for design, computer-aided design systems (CAD FPGA) must be used.

In what cases is it advisable to use FPGAs?

When developing original equipment, as well as to replace conventional electronic circuits of small and medium degree of integration. At the same time, the size of the device is significantly reduced, power consumption is reduced and reliability is increased. The most effective use of FPGAs in products requiring non-standard circuitry solutions. Designing a digital clock on FPGAs reduces the time spent on debugging. The number of elements used, integrated circuits, and memory blocks.

The whole process of creating a watch is reduced to the following point:

1. Choosing an FPGA model.
2. Writing a FPGA control program using the VHDL language tool.
3. Debugging the program on the debug stand.
4. Creation of the concept of batteries and indications.

Functional diagram

The functional part of the watch is shown in Fig. 1, where the hours and minutes or minutes and seconds are displayed on 4 seven segment indicators, depending on the state of the “Other” button.

The “Reset” button is designed to reset the seconds counter, depending on its value, if more than 30 then 1 minute is added and seconds are reset, if less then seconds are simply reset. The “Hour” and “Min” buttons are used to set the clock (by pressing).

Also, to implement a watch, a quartz generator is required which is designed to produce a fixed frequency with high temperature and time stability, low phase noise, and frequency stability of about (10-5 -10-12).

The structural diagram of the clock and a description of its work

When drawing up the structural diagram of Fig. 2, we take into account that the user should be able to reset seconds, set the hours and minutes, as well as the display mode of the two options, hour / min or min / sec.

When designing, it was decided to use a quartz pulse generator with a frequency of 27 MHz. Since the current frequency guarantees a high accuracy of counting seconds.

From quartz, a signal is sent to the divider unit, which in turn converts the signal with a frequency of 27 MHz into a clock signal of the meander type with a frequency of 1 Hz. Which in turn means that in 1 second one period of oscillation will pass.

Then the signal from the divider is fed to the first counter (second counter), which also receives a reset command, the counter analyzes the inputs, and then counts from 0 to 59. Each cycle, sending its state to the decoder. Upon reaching 59 (maximum count), or if “Reset” was pressed when the account status is greater than or equal to 30, it sends a meander-type clock pulse to the tracking counter.

The second counter (minute counter) works similarly to the first, except that the input signal is not “Reset” but “Min” (setting the minutes). As a result of this, 1 is added to the current account state, which contributes to an increase in the account.

The third counter (hour counter), receiving a signal from the leading counter and from “Hour” (Setting the clock), counts from 0 to 23. Each counter sends the counter value to the decoder.

The decoder, processing the signal from the “Other” button (display mode), selects the necessary input signals: for min / sec selects the values ​​of the first and second counter, for hours / min selects the values ​​of the second and third counter. It decrypts them and then encrypts them into a signal, necessary for displaying time numbers on a block of four 7-segment indicators.

Project development, hours in VHDL

When developing a program on VHDL, it was decided to use the structure using components. That allows us to write a program to execute each block of the structural diagram separately, it is also possible to combine several blocks into one component. It should be noted that the pressed position of the button is '0', and the pressed '1'.

Consider a component called timeMS, this is a universal component, it is used for seconds and minutes, since they seem to be.

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
Entity timeMS is
C: in std_logic; - +1 minute
R: in std_logic; - reset for sec.
Clk: in std_logic; - clock signal 1 sec.
M: out std_logic; - pass +1 on
hex: out std_logic_vector (0 to 5) - output to a seven-bit indicator
end timeMS;
Architecture behavior of timeMS is
signal cl: std_logic;
Process (clk, R, C)
Variable nex: integer range 0 to 59;
cl <= clk or not;
if R = '0'then
if nex> 29 then
M <= '1';
nex: = 0;
M <= '0';
nex: = 0;
end if;
if (cl'event and cl = '1') then
if nex = 59 then
nex: = 0;
M <= '1';
nex: = nex + 1;
M <= '0';
end if;
end if;
end if;
hex <= conv_std_logic_vector (nex, 6);
end process;
end behavior;

First, we declare the necessary packages, descriptions of the packages used. Then go to the description of the ports. As already mentioned earlier, this program combines two counters, as a result, the input ports for both the minute counter and second counter.

Input ports of the program:

- Port “C” - takes two values ​​('0' and '1') and is used to set the minutes.
- Port “R” - takes two values ​​('0' and '1') and is designed to reset seconds.
- “clk” port - a meander type clock signal, for seconds from a divider (see delitel add-ons), for minutes a signal from a leading second counter.
Input ports of the program:
- Port “M” - takes two values ​​('0' and '1'), sends a clock signal when the maximum count is reached, to the next counter.
- “hex” port - a 6-bit vector for sending the state of the counter to the decoder (for the hexMS component, see the supplement).

The process is “sensitive” to signal changes: clk, C, R. It is also a process with asynchronous reset, in the case of seconds, and asynchronous addition of +1 to the account in the case of minutes. An integer variable of type integer from 0 to 59 is used for the calculation.

At the beginning of the process, the clock signal and the signal from the “Min” button are added, then it is checked:
“Reset” = '0' conditions are checked , the current values ​​of the account are greater than 29; if not, then just zero, otherwise zero and send '1' to port M.

"Reset" = '1' it is checked whether the leading edge of the clock pulse has arrived. Then check the conditions for filling the counter, and record +1 in it.

At the end of the program, the values ​​of the nex variable are converted and sent to the hex port.

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