Faster, higher, stronger, or how to quickly digitize an analog signal
Once I came across an order to digitize a signal. The signal sampling rate was 50kHz. I quickly dealt with this task using a manual from the Internet. However, the customer was unable to squeeze out what he wanted from this speed and decided to announce an order for a frequency of 50 MHz. Due to the fact that the signal change frequency from 0 to 5V was no more than 10 MHz, I decided that I shouldn’t bother about the skin effect and took up the order.
Speed data was new to me, and I took two weeks to study the material. My favorite rule - not to solve the problem only from what lies beneath my feet helped me a lot.
Due to the fact that most of my work was related to the use of stm32F1XX, I began to study the possibility of working with this particular manufacturer. The first thing I dismissed is stm32f4XX. The fact is that even with the simultaneous coordinated operation of three high-speed ADCs, the sampling frequency will be no more than 7.2 MHz.
To start, I chose the ADC: AD6645. This series can work with a sampling frequency of up to 120 MHz. I chose at 80 MHz: AD6645-80. Now two unsolved problems remain:
- how to tact;
- how to receive a signal.
Option 1. FPGA.
Pros:
- works fast;
- flexibly changes.
Cons:
- expensive, what I needed was from $ 500 apiece;
- large dimensions, from 200 legs and a width of 30 mm on dyganali;
- unfamiliar environment and principles of work for me.
In this regard, the device is small then the final decision was precisely because of the dimensions.
Option 2. TTL / HCMOS generator + FIFO /
Pros:
- you can use any end receiver, even an 8 bit processor;
- In sum, cheaper than FPGA.
Cons:
- more details and consequently more connections of high-frequency digital signals.
After weighing the pros and cons, I began to look for details. Many will be asked why the search is right away. Yes, because a lot of things work at such frequencies, either very expensive, or 3-5 months, the delivery time, or a batch of 100 pcs (the price for one piece is from $ 50).
Total:
- ADC AD6645;
- IDT72V06;
- FXO - HC 5 3 6 R;
- STM32F103RET8.
The principle of operation:
1. The processor turns on the FXO – HC536R generator for 1 ms
2. The generator clocks the AD6645 ADC operation. On the leading edge of the generator, the ADC begins to digitize.
3. At the end of the work, the ADC sets a low level on the leg DRY.
4. Leg –W FIFO is connected to the DRY ADC leg. When a low ADC front appears on the leg, DRY FIFO writes data to internal memory.
5. Next, the processor takes data from the FIFO.
The connection diagram is shown in the figure.
Thank you for attention.
Speed data was new to me, and I took two weeks to study the material. My favorite rule - not to solve the problem only from what lies beneath my feet helped me a lot.
Due to the fact that most of my work was related to the use of stm32F1XX, I began to study the possibility of working with this particular manufacturer. The first thing I dismissed is stm32f4XX. The fact is that even with the simultaneous coordinated operation of three high-speed ADCs, the sampling frequency will be no more than 7.2 MHz.
To start, I chose the ADC: AD6645. This series can work with a sampling frequency of up to 120 MHz. I chose at 80 MHz: AD6645-80. Now two unsolved problems remain:
- how to tact;
- how to receive a signal.
Option 1. FPGA.
Pros:
- works fast;
- flexibly changes.
Cons:
- expensive, what I needed was from $ 500 apiece;
- large dimensions, from 200 legs and a width of 30 mm on dyganali;
- unfamiliar environment and principles of work for me.
In this regard, the device is small then the final decision was precisely because of the dimensions.
Option 2. TTL / HCMOS generator + FIFO /
Pros:
- you can use any end receiver, even an 8 bit processor;
- In sum, cheaper than FPGA.
Cons:
- more details and consequently more connections of high-frequency digital signals.
After weighing the pros and cons, I began to look for details. Many will be asked why the search is right away. Yes, because a lot of things work at such frequencies, either very expensive, or 3-5 months, the delivery time, or a batch of 100 pcs (the price for one piece is from $ 50).
Total:
- ADC AD6645;
- IDT72V06;
- FXO - HC 5 3 6 R;
- STM32F103RET8.
The principle of operation:
1. The processor turns on the FXO – HC536R generator for 1 ms
2. The generator clocks the AD6645 ADC operation. On the leading edge of the generator, the ADC begins to digitize.
3. At the end of the work, the ADC sets a low level on the leg DRY.
4. Leg –W FIFO is connected to the DRY ADC leg. When a low ADC front appears on the leg, DRY FIFO writes data to internal memory.
5. Next, the processor takes data from the FIFO.
The connection diagram is shown in the figure.
Thank you for attention.