December 2, 2013 at 00:11Simple SDR FPGA receiver
In this article I will talk about how to make a fairly simple HF SDR receiver based on the DE0-nano debug board.
An example of received signals: You can read about SDR technology here . In short, this is a radio signal reception technique in which a large amount of information processing is performed in digital form. Thanks to the use of FPGAs and a high-speed ADC, it is possible to make a receiver in which even the downward frequency transfer is performed digitally. This method is called DDC (Digital Down Conversion), more about it can be read here and here (more theory) . Using this technique, you can greatly simplify the receiver, in which the only analog part is the ADC. And now in more detail about my receiver.
It is based on Altera FPGAs installed on the DE0-Nano debug board. The fee is relatively cheap ($ 60 for students), however, with a fairly expensive delivery ($ 50). Now it is becoming more and more popular with radio amateurs who are starting to get acquainted with FPGAs.
The main task of FPGAs is to “capture” a digital signal from the ADC, transfer it to the low-frequency region, filter it and send the result to a computer. The block diagram of the receiver, implemented by me, has the following form: Let us consider in sequence the components that the radio signal and digital information pass through.
Radio amateurs have the saying, “A good antenna is the best amplifier.” Indeed, a lot depends on the antenna. Most of the most interesting shortwave signals cannot be received on a simple antenna (for example, on a piece of wire). There are no special problems outside the city - a sufficiently long wire can work as a good antenna (for reception). In the city, especially inside large reinforced concrete houses, everything is much worse - a long antenna cannot be stretched, and there are a lot of disturbing noises (household appliances can create a very high noise level on the air), so choosing an antenna becomes difficult.
To receive radio signals, I use an active frame antenna, the design of which is described here .
My antenna looks like this:
In fact, the antenna is a large oscillatory circuit (the capacitor is inside the box on the table). It is installed on the balcony, and works pretty well. The main advantage of the loop antenna is that due to the use of the resonance phenomenon, it allows you to suppress noise at unused frequencies, but there is also a drawback - when changing from one frequency range to another, you need to rebuild it.
Choosing an ADC is not easy either. The ADC must have high bit depth to increase the dynamic range, and for the DDC receiver, it must also have high speed. Usually ADCs with 16-bit resolution and speed> 50 MSPS are installed in good DDC receivers. However, the cost of such ADCs is more than $ 50, and I wanted to put something simpler in the experimental design.
I chose the AD9200 - a 10-bit 20 MSPS ADC worth 200 rubles. These are very mediocre characteristics for a DDC receiver, however, as practice has shown, the ADC is quite suitable for receiving signals.
The ADC is installed on a separate board, which is inserted into the debug board : The bottom of the board is metallized, the metal layer is connected to the ADC ground, which also protects against interference.
Since the ADC digitizes only signals of a positive level, and the signal from the antenna is bipolar, the signal has to be shifted by half the reference voltage (for this resistors R1 and R2 are used). The artificially created constant component is then subtracted from the digital signal in the FPGA.
All further signal processing after the ADC goes to the FPGA.
The data stream with the ADC is 200 Mbps (10-bit x 20 MSPS). It is very difficult to transfer such a stream directly to a computer, and then it is also very difficult to process, so the signal frequency must be specially reduced. When transferring to a lower frequency, the phenomenon of a “mirror channel” occurs, to combat which a quadrature frequency conversion is used - the signal is converted into a complex form (division into two I / Q channels occurs). Transfer to a lower frequency is done by multiplying the original signal by the signal of the generator. The FPGA used has enough hardware multipliers, so this is not a problem.
In order to transfer the input signal to the desired frequency, it must be created. For this, the ready-made Quartus component is used - NCO (numerically controlled oscillator). The clock frequency, the same as that of the ADC (20 MHz), is supplied to the generator, a value that determines the frequency is supplied to its control input, and a digital sinusoidal signal of the desired frequency is generated at its output, sampled at a frequency of 20 MHz. NCO is capable of simultaneously generating a cosine signal, so that a quadrature signal can be generated.
After mixing with the generator signal from the output of the multipliers, the signal comes out already transferred to a lower frequency, but still with a high sampling frequency (20 MSPS). The signal needs to be decimated , i.e., part of the samples should be discarded. It’s impossible to discard unnecessary samples just like that, as this will lead to distortion of the output signal. Therefore, the signal must be passed through a special filter (CIC filter). In this case, I wanted to get a signal sampling frequency of 50 kHz at the output of the receiver. It follows that the frequency should be reduced (20e6 / 50e3 = 400) times. Decimation will have to be done in 2 stages - first 200, then 2 times.
The first step is the CIC filter. I used a 5-stage filter.
As a result of operation, the CIC filter increases the bit depth of the output signal by lowering the signal bandwidth. With my receiver, I artificially limited it to 16 bits.
Since there are two channels in the receiver, two filters will also be required.
Unfortunately, the CIC filter has a rather steep frequency response, tending to 0 when approaching the output sampling frequency (100 kHz). To compensate for its curvature, the following filter is used.
This filter is needed in order to compensate for the decrease in the frequency response of the CIC filter and perform another decimation step (twice). Altera has already taken care of the calculation method of this filter - when creating a CIC filter, a program for Matlab is automatically generated, running which you can generate coefficients for the compensation filter.
The frequency response of CIC, FIR and the resulting result (the same program for Matlab builds the graphs): It can be seen that at a frequency of 25 kHz the CIC filter will attenuate the signal by 20 dB, which is very much, but using the FIR filter, the attenuation is only 10 dB, and at lower frequencies, attenuation is practically absent. At the output of the FIR filter, taking into account decimation, there will be a sampling frequency of the signal of 50 kHz.
Why was it impossible to immediately decimulate the signal 400 times? This is due to the fact that the cutoff frequency of the FIR filter should be 1/4 of its output. In this case, the sampling frequency at the filter output without decimation, as at its input, is 100 kHz. As a result of this, the cutoff frequency will be just 25 kHz, which can be seen in the graphs above.
Both filters are prefabricated Quartus components.
The received data stream ((16 + 16) bit x 50 KSPS = 1.6 Mbit) must be transferred to the computer. I decided to transfer data via Ethernet. There is no such interface on the debug board. It would be most correct to make a separate board with a PHY controller, start the Nios soft processor, and transfer data through them. However, this greatly complicates the design. I went the simpler way - Ethernet packets can be formed on the FPGA itself, so you can transfer data at a speed of 10 Mbit. In this case, the Ethernet cable is connected to the FPGA terminals through an isolation transformer. Projects with this principle of operation can be viewed here and here .
As a basis, I chose the first project, partially finalizing it. In the initial project, the FPGA sends a specific UDP packet to the computer with the specified IP and MAC address. After the alteration, the Ethernet module of the transmitter could transmit 1024 bytes, reading them from RAM. As a result, 256 pairs of 16-bit signal values taken from the filter outputs are sent to the computer in one packet. Since the data is received from the ADC continuously, and you need to send it to the computer in batches, I had to implement double memory buffering - while one RAM is filling up, data from another RAM is transmitted via Ethernet. After the first RAM is full, both RAMs "swap", for which a fairly simple control module is responsible.
Since the data at the output of the filters is transmitted by a stream from a pair of 16 bit values, and individual bytes are transmitted via Ethernet, a module has been introduced to convert the streams to the structure, which converts a 32 bit 50 KSPS stream to 8 200 KSPS bit.
As it turned out, if you transmit a data stream with a speed of 1.6 Mbit, then the device to which the receiver is connected does not even detect it (no link). This is due to the fact that the data packets are transmitted with a period of approximately 5 ms, and in order to tell the other network device the connection speed (10 Mbit), you need to transmit a special short pulse (NLP) every 8-24 ms. Due to the high frequency of packet transmission, the Ethernet module does not have time to transmit these pulses, and Autonegotiation does not occur.
Therefore, in order for the opposite device to still be able to determine the connection speed, it is sufficient to temporarily reduce the packet transmission frequency (by 4 times) when the receiver is turned on, due to which the Ethernet module manages to transmit NLP pulses.
In order to control the receiver (set the tuning frequency), a certain value must be transmitted to it, which will be used to set the NCO frequency.
To receive this value, the component from the above site is also used, modified to receive data, and output them in the form of a 24 bit number. Since the receiver and transmitter modules are in no way connected with each other, it is impossible to implement ARP, and in fact this means that the receiver will not have an IP and MAC address. You can transmit information to it if you send a broadcast packet to the network.
Physically, as in the case of the transmitter, the network wire is connected to the debug board through a transformer. However, here it is no longer possible to connect to arbitrary FPGA outputs, since the signal is quite small. You need to use pins that support the LVDS interface - it is differential.
Resources used by the FPGA program:
- 5006 LE
- 68 9-bit multipliers (64 of them are used in the FIR filter).
- 16.826 bit memory (8 M9K blocks).
Quartus project project view:
After the computer has received the data, it needs to be processed. It is best to take a ready-made program. Typically, in SDR programs they implement the necessary digital filters, algorithms designed to form the sound and filter it, the FFT of the received signal, the construction of its spectrum and “waterfall”.
I use the HDSDR and SDRSharp programs, both of which support data input using the same ExtIO libraries (Winrad program format). Library software requirements are well documented .
Right hereThere is an example of creating such a library. I redid this example, added to it the reception of data from the network, gluing two packets (the program crushes at least 512 pairs of I / Q samples at a time), sending them to the program, and transmitting a broadcast packet with the calculated value for NCO when changing the frequency in the program. Before that, I had never had to create libraries, and in C ++ I am not strong, so it can be written in the library not at all optimally.
Since the sampling frequency of the I / Q signals at the output of the receiver filters is 50 kHz, a band of 50 kHz will be available for review in the reception program. (± 25 kHz of the frequency generated by the NCO).
The assembled receiver looks like this: A resistor connects the midpoints of the transformer to a 3.3 V board - this improves the reception and transmission of data over the network.
After the receiver was completely assembled and all the programs were written, it turned out that the sensitivity is not enough. Even an active antenna received only broadcasting radio stations and signals from amateur radio fans operating at high power.
As I understand it, this is due to the low ADC capacity. To increase the sensitivity, I had to make an additional amplifier on the BF988 transistor (located inside a small metal box). The amplifier was able to significantly increase the sensitivity of the receiver.
Appearance of the whole structure:
The power supply unit provides a voltage of 12 V for powering the antenna amplifier; in a metal round box there are several band-pass filters that reduce out-of-band signals, which improves signal prim. I note that in many cases, reception is possible without DFT.
Now about what can be taken on HF. Despite the rather high noise level, it is possible to receive quite a lot of signals, broadcast radio stations are well received, amateur radio receivers are not bad.
An example of receiving signals in the HDSDR program (reception was carried out during the CQ WW DX Contest): Video reception:
Able to receive WSPRnet signals. WSPRnet is a network of amateur beacons that automatically exchange short messages with each other. Data from lighthouses is automatically published on the Internet. In this case, by installing a special program, you can decode the received signals and send them to the network. The site has the opportunity to see a map on which the links between the beacons for a certain time interval are shown.
Here's what I got for half a day of admission:
An important feature of WSPR is the very small transmitter power (less than 5 W), a narrow band of the transmitted signal, and a long transmission duration of one message (2 min). Thanks to digital processing in the decoder program, very weak signals can be received. I was able to receive the signal of a 100 mW lighthouse located at a distance of ~ 2000 km.
Ham enthusiasts using the JT65. JT65 is one of the digital communication protocols between hams. As in the WSPR, it uses low power and long transmission (1 min). Messages are automatically received, so you can leave the receiver for a long time, and then see who managed to receive.
Reception example:
Digital Broadcasting (DRM). Some broadcast radio stations transmit sound digitally. It is not easy to receive such signals in a city - there is not enough signal level. One station could be received : There are many other radio signals that would be interesting to receive. There are also weather faxes, the RBU exact time station (at a marvelous frequency of 66.6 kHz), and others. Project for Quartus + source code and ExtIO dll itself
An example of received signals: You can read about SDR technology here . In short, this is a radio signal reception technique in which a large amount of information processing is performed in digital form. Thanks to the use of FPGAs and a high-speed ADC, it is possible to make a receiver in which even the downward frequency transfer is performed digitally. This method is called DDC (Digital Down Conversion), more about it can be read here and here (more theory) . Using this technique, you can greatly simplify the receiver, in which the only analog part is the ADC. And now in more detail about my receiver.
It is based on Altera FPGAs installed on the DE0-Nano debug board. The fee is relatively cheap ($ 60 for students), however, with a fairly expensive delivery ($ 50). Now it is becoming more and more popular with radio amateurs who are starting to get acquainted with FPGAs.
The main task of FPGAs is to “capture” a digital signal from the ADC, transfer it to the low-frequency region, filter it and send the result to a computer. The block diagram of the receiver, implemented by me, has the following form: Let us consider in sequence the components that the radio signal and digital information pass through.
Antenna
Radio amateurs have the saying, “A good antenna is the best amplifier.” Indeed, a lot depends on the antenna. Most of the most interesting shortwave signals cannot be received on a simple antenna (for example, on a piece of wire). There are no special problems outside the city - a sufficiently long wire can work as a good antenna (for reception). In the city, especially inside large reinforced concrete houses, everything is much worse - a long antenna cannot be stretched, and there are a lot of disturbing noises (household appliances can create a very high noise level on the air), so choosing an antenna becomes difficult.
To receive radio signals, I use an active frame antenna, the design of which is described here .
My antenna looks like this:
In fact, the antenna is a large oscillatory circuit (the capacitor is inside the box on the table). It is installed on the balcony, and works pretty well. The main advantage of the loop antenna is that due to the use of the resonance phenomenon, it allows you to suppress noise at unused frequencies, but there is also a drawback - when changing from one frequency range to another, you need to rebuild it.
ADC
Choosing an ADC is not easy either. The ADC must have high bit depth to increase the dynamic range, and for the DDC receiver, it must also have high speed. Usually ADCs with 16-bit resolution and speed> 50 MSPS are installed in good DDC receivers. However, the cost of such ADCs is more than $ 50, and I wanted to put something simpler in the experimental design.
I chose the AD9200 - a 10-bit 20 MSPS ADC worth 200 rubles. These are very mediocre characteristics for a DDC receiver, however, as practice has shown, the ADC is quite suitable for receiving signals.
The ADC is installed on a separate board, which is inserted into the debug board : The bottom of the board is metallized, the metal layer is connected to the ADC ground, which also protects against interference.
ADC connection diagram
I do not have the experience of wiring RF designs, so it is possible that the circuit and wiring can be improved.
I do not have the experience of wiring RF designs, so it is possible that the circuit and wiring can be improved.
Since the ADC digitizes only signals of a positive level, and the signal from the antenna is bipolar, the signal has to be shifted by half the reference voltage (for this resistors R1 and R2 are used). The artificially created constant component is then subtracted from the digital signal in the FPGA.
All further signal processing after the ADC goes to the FPGA.
The data stream with the ADC is 200 Mbps (10-bit x 20 MSPS). It is very difficult to transfer such a stream directly to a computer, and then it is also very difficult to process, so the signal frequency must be specially reduced. When transferring to a lower frequency, the phenomenon of a “mirror channel” occurs, to combat which a quadrature frequency conversion is used - the signal is converted into a complex form (division into two I / Q channels occurs). Transfer to a lower frequency is done by multiplying the original signal by the signal of the generator. The FPGA used has enough hardware multipliers, so this is not a problem.
Nco
In order to transfer the input signal to the desired frequency, it must be created. For this, the ready-made Quartus component is used - NCO (numerically controlled oscillator). The clock frequency, the same as that of the ADC (20 MHz), is supplied to the generator, a value that determines the frequency is supplied to its control input, and a digital sinusoidal signal of the desired frequency is generated at its output, sampled at a frequency of 20 MHz. NCO is capable of simultaneously generating a cosine signal, so that a quadrature signal can be generated.
Cic filter
After mixing with the generator signal from the output of the multipliers, the signal comes out already transferred to a lower frequency, but still with a high sampling frequency (20 MSPS). The signal needs to be decimated , i.e., part of the samples should be discarded. It’s impossible to discard unnecessary samples just like that, as this will lead to distortion of the output signal. Therefore, the signal must be passed through a special filter (CIC filter). In this case, I wanted to get a signal sampling frequency of 50 kHz at the output of the receiver. It follows that the frequency should be reduced (20e6 / 50e3 = 400) times. Decimation will have to be done in 2 stages - first 200, then 2 times.
The first step is the CIC filter. I used a 5-stage filter.
As a result of operation, the CIC filter increases the bit depth of the output signal by lowering the signal bandwidth. With my receiver, I artificially limited it to 16 bits.
Since there are two channels in the receiver, two filters will also be required.
Unfortunately, the CIC filter has a rather steep frequency response, tending to 0 when approaching the output sampling frequency (100 kHz). To compensate for its curvature, the following filter is used.
Compensation FIR Filter
This filter is needed in order to compensate for the decrease in the frequency response of the CIC filter and perform another decimation step (twice). Altera has already taken care of the calculation method of this filter - when creating a CIC filter, a program for Matlab is automatically generated, running which you can generate coefficients for the compensation filter.
The frequency response of CIC, FIR and the resulting result (the same program for Matlab builds the graphs): It can be seen that at a frequency of 25 kHz the CIC filter will attenuate the signal by 20 dB, which is very much, but using the FIR filter, the attenuation is only 10 dB, and at lower frequencies, attenuation is practically absent. At the output of the FIR filter, taking into account decimation, there will be a sampling frequency of the signal of 50 kHz.
Why was it impossible to immediately decimulate the signal 400 times? This is due to the fact that the cutoff frequency of the FIR filter should be 1/4 of its output. In this case, the sampling frequency at the filter output without decimation, as at its input, is 100 kHz. As a result of this, the cutoff frequency will be just 25 kHz, which can be seen in the graphs above.
Both filters are prefabricated Quartus components.
Transferring data to a computer
The received data stream ((16 + 16) bit x 50 KSPS = 1.6 Mbit) must be transferred to the computer. I decided to transfer data via Ethernet. There is no such interface on the debug board. It would be most correct to make a separate board with a PHY controller, start the Nios soft processor, and transfer data through them. However, this greatly complicates the design. I went the simpler way - Ethernet packets can be formed on the FPGA itself, so you can transfer data at a speed of 10 Mbit. In this case, the Ethernet cable is connected to the FPGA terminals through an isolation transformer. Projects with this principle of operation can be viewed here and here .
As a basis, I chose the first project, partially finalizing it. In the initial project, the FPGA sends a specific UDP packet to the computer with the specified IP and MAC address. After the alteration, the Ethernet module of the transmitter could transmit 1024 bytes, reading them from RAM. As a result, 256 pairs of 16-bit signal values taken from the filter outputs are sent to the computer in one packet. Since the data is received from the ADC continuously, and you need to send it to the computer in batches, I had to implement double memory buffering - while one RAM is filling up, data from another RAM is transmitted via Ethernet. After the first RAM is full, both RAMs "swap", for which a fairly simple control module is responsible.
Since the data at the output of the filters is transmitted by a stream from a pair of 16 bit values, and individual bytes are transmitted via Ethernet, a module has been introduced to convert the streams to the structure, which converts a 32 bit 50 KSPS stream to 8 200 KSPS bit.
As it turned out, if you transmit a data stream with a speed of 1.6 Mbit, then the device to which the receiver is connected does not even detect it (no link). This is due to the fact that the data packets are transmitted with a period of approximately 5 ms, and in order to tell the other network device the connection speed (10 Mbit), you need to transmit a special short pulse (NLP) every 8-24 ms. Due to the high frequency of packet transmission, the Ethernet module does not have time to transmit these pulses, and Autonegotiation does not occur.
Therefore, in order for the opposite device to still be able to determine the connection speed, it is sufficient to temporarily reduce the packet transmission frequency (by 4 times) when the receiver is turned on, due to which the Ethernet module manages to transmit NLP pulses.
Receive data from a computer
In order to control the receiver (set the tuning frequency), a certain value must be transmitted to it, which will be used to set the NCO frequency.
To receive this value, the component from the above site is also used, modified to receive data, and output them in the form of a 24 bit number. Since the receiver and transmitter modules are in no way connected with each other, it is impossible to implement ARP, and in fact this means that the receiver will not have an IP and MAC address. You can transmit information to it if you send a broadcast packet to the network.
Physically, as in the case of the transmitter, the network wire is connected to the debug board through a transformer. However, here it is no longer possible to connect to arbitrary FPGA outputs, since the signal is quite small. You need to use pins that support the LVDS interface - it is differential.
Resources used by the FPGA program:
- 5006 LE
- 68 9-bit multipliers (64 of them are used in the FIR filter).
- 16.826 bit memory (8 M9K blocks).
Quartus project project view:
Processing data on a computer
After the computer has received the data, it needs to be processed. It is best to take a ready-made program. Typically, in SDR programs they implement the necessary digital filters, algorithms designed to form the sound and filter it, the FFT of the received signal, the construction of its spectrum and “waterfall”.
I use the HDSDR and SDRSharp programs, both of which support data input using the same ExtIO libraries (Winrad program format). Library software requirements are well documented .
Right hereThere is an example of creating such a library. I redid this example, added to it the reception of data from the network, gluing two packets (the program crushes at least 512 pairs of I / Q samples at a time), sending them to the program, and transmitting a broadcast packet with the calculated value for NCO when changing the frequency in the program. Before that, I had never had to create libraries, and in C ++ I am not strong, so it can be written in the library not at all optimally.
Since the sampling frequency of the I / Q signals at the output of the receiver filters is 50 kHz, a band of 50 kHz will be available for review in the reception program. (± 25 kHz of the frequency generated by the NCO).
The assembled receiver looks like this: A resistor connects the midpoints of the transformer to a 3.3 V board - this improves the reception and transmission of data over the network.
After the receiver was completely assembled and all the programs were written, it turned out that the sensitivity is not enough. Even an active antenna received only broadcasting radio stations and signals from amateur radio fans operating at high power.
As I understand it, this is due to the low ADC capacity. To increase the sensitivity, I had to make an additional amplifier on the BF988 transistor (located inside a small metal box). The amplifier was able to significantly increase the sensitivity of the receiver.
Appearance of the whole structure:
The power supply unit provides a voltage of 12 V for powering the antenna amplifier; in a metal round box there are several band-pass filters that reduce out-of-band signals, which improves signal prim. I note that in many cases, reception is possible without DFT.
Now about what can be taken on HF. Despite the rather high noise level, it is possible to receive quite a lot of signals, broadcast radio stations are well received, amateur radio receivers are not bad.
An example of receiving signals in the HDSDR program (reception was carried out during the CQ WW DX Contest): Video reception:
Able to receive WSPRnet signals. WSPRnet is a network of amateur beacons that automatically exchange short messages with each other. Data from lighthouses is automatically published on the Internet. In this case, by installing a special program, you can decode the received signals and send them to the network. The site has the opportunity to see a map on which the links between the beacons for a certain time interval are shown.
Here's what I got for half a day of admission:
An important feature of WSPR is the very small transmitter power (less than 5 W), a narrow band of the transmitted signal, and a long transmission duration of one message (2 min). Thanks to digital processing in the decoder program, very weak signals can be received. I was able to receive the signal of a 100 mW lighthouse located at a distance of ~ 2000 km.
Ham enthusiasts using the JT65. JT65 is one of the digital communication protocols between hams. As in the WSPR, it uses low power and long transmission (1 min). Messages are automatically received, so you can leave the receiver for a long time, and then see who managed to receive.
Reception example:
Digital Broadcasting (DRM). Some broadcast radio stations transmit sound digitally. It is not easy to receive such signals in a city - there is not enough signal level. One station could be received : There are many other radio signals that would be interesting to receive. There are also weather faxes, the RBU exact time station (at a marvelous frequency of 66.6 kHz), and others. Project for Quartus + source code and ExtIO dll itself