Analysis of digital circuits for failure risks

    The Boolean algebra used to simulate the operation of digital circuits does not take into account the transition time (or inertia) of logical elements (for example, “AND”, “OR”) from one state to another (for example, from 0 to 1). In cases where the propagation time of the signal inside the element is sufficiently short, the transition delay can be ignored. But with an increase in the frequency of change of input signals in real circuits, the influence of the propagation time of the signal inside its elements begins to affect. Such delays can give rise to unstable operation of devices (i.e., in signals after successive passage through circuit nodes, transitions that are not considered by the model of the circuit appear, called faults) Many manufacturers of modern processors keep secret how they deal with failures caused by delays at frequencies of the order of GHz. After all, an ordinary conductor with many close bends on the board in this mode of operation is already turning into inductance.

    To analyze the simplest schemes for the risks of failure, they usually use the time chart method, which has already become classic. The signals in each node are drawn strictly under each other; where necessary, an artificial delay is made in the transition from one state to another, and then the output signals are constructed according to the Boolean representation. This method is not good in that it requires working with charts, which can introduce an error into the received signals. And we need to know whether the failure will occur, and what it will look like.

    In 2005, I touched on this topic and expressed my thoughts in this article in English. However, my good friend advised me to write in Habrahabr for discussion with users.

    In this topic, the procedure for analyzing circuits is transferred from a graphical representation to a mathematical representation. In this case, the parameter “time” is introduced into the Boolean algebra by replacing the logical operations with arithmetic ones. For simplicity of analysis, asynchronous ones are considered, i.e. uncontrolled by an external (synchronizing or timing) signal, digital circuits.

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    1. The transition from the logical representation of Boolean functions to the arithmetic representation


    Consider a numerical set image. It defines the operations of negation, conjunction, disjunction and produced from them (for example, implication, alternative disjunction, etc.). We express these logical operations in terms of arithmetic operations on the set M :
    (1)image

    Let us show the validity of de Morgan's law image:
    image

    To expressions (1), add rule
    (2)image
    for all natural values ​​of m , the validity of which is obvious.

    The expression for the Boolean function, which is a function of the input signals of the circuit, can now be simplified according to the laws of arithmetic operations and rule (2). After simplifications, go back to the Boolean representation. At the same time, the minimization process itself can be automated by switching to symbolic calculations.

    2. Entering the “time” parameter into the Boolean algebra


    As you know, a unit step function or Heaviside function is defined on the set of real numbers and returns a number belonging to the set M :
    image

    Denote by t the current time. Note that the function h is also called the switching function. The following statement is obvious: any signal in a logic circuit that includes a transition from one logical state to another can be represented as the sum-difference of the Heaviside functions taken with the corresponding argument.

    For the function h, there is an obvious rule
    (3)image
    where imageis the point in time when the signal changes. Add rule (3) to (1) and (2).

    Now, knowing the analytical expression for the input signals of the logic circuit, one can find the form of the function of the output signal.

    3. Delays in the logic elements of the circuit


    It is convenient to model the signal delay in the logic element as the difference between the argument of the Heaviside function and the duration of the delay (since for the existing logic elements, delays in the edge (transition from 0 to 1) and the fall (transition from 1 to 0) are basically the same). Thus, any real logic element of the circuit can be modeled as a series connection of a link of "pure" delay for each input and an ideal logical element (here, the delay is equal to the duration of the delay). For example, the equation of the output signal of the conjunctor with an imageinput delay has the form
    image
    where imageand imageare functions describing the corresponding input signals.

    4. The algorithm for finding failed states


    The proposed algorithm for finding failed states is similar to the method of time diagrams; the advantage of the method is that we do not work with graphic images of signals, but with their analytical expressions (in this case, it becomes possible to analytically evaluate the time characteristics of a failure):
    1. Let the circuit under study function in accordance with some logical expression specified by the DNF;
    2. We define the functions of the input signals, which are transitions in the truth table, expressed through the Heaviside function;
    3. We follow the path of the signals in the logic circuit in order to search for the expression for the output signal of the circuit, applying rules (1) and (3);
    4. If the resulting expression contains the Heaviside function difference, then we have a static failure; if a Heaviside function with a delay argument is present, then the failure is dynamic.

    5. An example of a logical circuit analysis.


    We study the transition from set 1111 to set 1001 of the truth table for the circuit shown in Fig. 1.
    image
    Fig. 1. A circuit that implements a Boolean function image.

    We represent the input signals as follows (for simplicity, we consider the change in state at a time instant equal to 5 time units):
    image

    Suppose that all elements have the same delays equal image. Then
    image

    Thus, we got a static failure - the difference between the Heaviside functions (Fig. 2) enters the resulting expression.
    image
    Fig. 2. The graph of the signal Y ( t ).

    Conclusion


    In the topic, a method for analyzing digital circuits for failure risks was considered using the analytical representation of the signals inside the circuit. In this case, it was necessary to replace the logical operations with arithmetic ones. Transitions from one signal state to another were described by the Heaviside function. The advantage of the described modification of the method of time diagrams is that it is possible to analytically analyze the characteristics of the failure.

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