Three-dimensional integration: what are the difficulties?

    KDPV on the right is a miniature camera (62.5 thousand pixels), made possible by connecting to an optical sensor via TSV.

    In one of the previous posts , I talked about what is three-dimensional integration and how this technology could extend the life of silicon electronics due to growth into the third dimension. This time I will try to describe the known problems of this technology, because of which now and in the next few years, “multi-story” microprocessors and a new generation of memory will not appear in stores. It is always easier to criticize reasonably than to praise :). So ...

    For starters - about making holesin a silicon wafer. The thickness of the silicon wafers used for lithography varies from ~ 20 to ~ 800 microns. In this case, the lower layer is usually in the category> 250 μm, and the rest in the category <60 μm. There are a number of reasons for this, including mechanical strength. So, the acute problem is how to make a lot of neat holes in a silicon layer even 20 microns thick, and at the same time not damage the wafer itself (it already contains or will contain transistors three orders of magnitude smaller). There are several technologies for making holes, and traditionally there is a choice between accuracy and speed, which means price. I will give a few images.

    Laser pulse (40ns, 100KHz) hole (9400 pcs./19 min.)

    Results of chemical etching of holes cut by a laser (20 min. / Plate)

    The next step is the metallization of the holes . Here, too, have a number of their problems.
    First, the dimensions of the TSV and transistors differ by 2-3 orders of magnitude, therefore, if you try to transfer such an amount of metal into the hole in the same ways, it will take a long time. Rather, LONG, and expensive.
    The second, due to the fact that the metal must not be applied on a flat surface, but on the inner walls of the hole, the holes tend to “grow”. That is, the metal completely closes the inlet, without completely covering its walls and without creating a through conductive connection. To solve this problem, additional efforts must be made.
    There are interesting approaches, such as “plugging” a metal pin into the holes, with obvious problems, both from the category of accuracy of operations and the safety of the plate.

    Next up are the problems of assembling a stack of silicon wafersusing TSV (vertical connections). 3d integration is primarily important for large devices, as could greatly reduce their cost by reducing the area of ​​the silicon wafer rejected by one single defect. But instead, the problem is changing: now when laying one plate on another, you need to connect hundreds and thousands of TSV contacts to each other. And to do this the first time, there will be no second attempt. Similar exercises with TSV sizes of the order of units or tens of microns lie in the field of precision mechanics, which has its own limitations. And the price of error is the marriage of the entire stack of plates. That will not positively affect the price.
    At the same time, around TSV during development, it is necessary to leave some “exclusion zone” free of transistors. Otherwise, the risk is too high that, in the process of cutting holes or assembling a stack of plates, the logic in this area will be damaged. On the one hand, this increases the occupied area, and on the other, it requires taking such things into account during the design process.
    The mechanical strength of such a product is a separate problem. The presence of through holes in itself reduces the strength of the plates. In addition, for reasons of load balancing, it would be better to have holes evenly spaced. Also, such a “sandwich” of silicon wafers will have uneven characteristics of thermal expansion. With differences in operating temperature, this creates a significant force at the TSV connection points and can lead to destruction of the stack.

    But the main problem, of course, is maintaining the temperature regime . In order to ensure a temperature below 80 degrees, you have to go to various tricks. For example, IBM experts propose alternating silicon wafers with wafers with high thermal conductivity, creating a kind of “penetrating radiator” that removes heat more efficiently than just touching the surface.
    In theory, there are no restrictions on how many plates can be combined using 3d integration. But, even for memory, where the problem with heat dissipation is not so acute, plans for the future are limited to eight layers.
    Temperature conditions are also the reason why 3d-integration technology was beyond Intel's interests, despite the fact that several other companies in the industry actively developed and tried to use it. Until relatively recently, the mobile device market was not a priority, and all efforts were aimed at creating desktop and server processors. At the same time, the main goal was to increase productivity, rather than reduce energy consumption. The greatest benefit could be obtained by applying 3d-integration to large chips, like the same Itanium. But temperature problems actively interfere with this.

    An interesting problem in some cases can be testing and debugging.similar devices. Imagine dividing into plates not as “processor separately, memory separately”, but something more interesting, where each plate is not a full-fledged device and does not work separately from the others. In such a situation, the question arises, how to check the functioning of each plate before stacking? If such a test is rejected, then the probability that the final device will not work due to plate connection errors will add the probability that one of the plates will not function.

    Well, the last, in order, and not in importance. The development of devices using 3d-integration requires appropriate support by means of design automation. A number of companies have been preoccupied with this for a long time, in particular, Synopsys has been working in this direction since at least 2009. But this is a long process. The efforts here are not limited to the developer’s man-hours, and much remains to be done.

    On this I will end. A huge number of more specific problems are hardly of interest to the general public. And the above should be enough to understand that 3d integration is not a “silver bullet” and there are a lot of problems on the way to it.
    Perhaps there will be another post on a number of exotic applications of 3d integration technology.

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