Class D Class Software Implementation
Best-404-Error asks if it is possible to get a compilation result of less than 512 bytes if the source code is written in a high-level language. You can, if you simplify the task assigned to the firmware.
The software implementation of a Class D amplifier allows you to change its parameters (PWM frequency, duty cycle at rest) by changing the firmware.
The hardware circuit of the device:
Input signals pass through capacitors to cut off the DC component, and then through resistor dividers, adding a new DC component of the order of +0.55 V. At the same time, the capacitors and lower resistors of the dividers form an HPF that cuts off frequencies below 28 Hz. Experience has shown that it is better to increase the cutoff frequency of these filters, because small distortions occur anyway.
The signals are fed to the first and third ADCs of the microcontroller. The reference voltage of the ADC is chosen equal to 1.1 V. The division ratio of the clock frequency is 16, so the ADCs operate at a frequency of 500 kHz. The interrupt routine cycles through the first and third ADCs. One of the read values is written to OCR1A, the second to OCR1B.
Timer 1 is configured so that the unit at the PWM outputs appears when these values coincide, and zero - when the timer is reset to zero. After tuning, this part of the algorithm is performed in hardware, but at the same time as the signal amplitude, it changes with respect to the originally set frequency and the PWM frequency.
If the duty cycle at rest is selected at 50 percent (better quality, but less cost-effective), low-pass filters are required in front of the dynamic heads.
Files: C ++ source, the compilation result of Atmel Studio 7.0 (it turned out 495 bytes), the scheme is in Eagle format , the board is in it , the G-code is for cutting through a drawing of a board , drilling it , cutting to size .
The board is single-sided:
Dynamic heads are connected via a standard dual H-bridge L293N:
Amplifier in action: