Additional Uplinks in Intel C620 System Logic Architecture

    In the architecture of x86-platforms two streams arose, mutually complementing each other. According to one version, it is necessary to move towards integration in a single chip of computing and control resources. The second approach is the distribution of responsibilities: the processor is equipped with a productive bus that forms a peripheral scalable ecosystem. It forms the basis of the Intel C620 system logic topology for high-level platforms.

    The fundamental difference from the previous Intel C610 chipset is to expand the communication channel of the processor with the peripherals that are part of the PCH chip through the use of PCIe links along with the traditional DMI bus.

    The difference between the Intel C620 and its predecessor in the use of PCIe-links with a DMI bus

    Let's take a closer look at the innovations of the Intel Lewisburg south bridge: what evolutionary and revolutionary approaches have expanded its powers in communication with processors?

    Evolutionary Changes in Communication CPU-PCH


    As part of the evolutionary approach, the main communication channel between the CPU and the south bridge, which is the Direct Media Interface (DMI) bus, received support for PCIe x4 Gen3 mode with a performance of 8.0 GT / S. Previously, in the Intel C610 PCH, the processor and system logic were communicating in PCIe x4 Gen 2 mode with 5.0 GT / S bandwidth.

    Comparison of Intel C610 and C620 System Logic Functionality

    Comparison of Intel C610 and C620 System Logic Functionality

    Note that this subsystem is much more conservative than the integrated processor PCIe ports, which are usually used to connect GPU and NVMe drives, where PCIe 3.0 has been used for a long time and the transition to PCI Express Gen4 is planned.

    Revolutionary Changes in Communication CPU-PCH


    The revolutionary changes include the addition of new PCIe-communication channels CPU-PCH, called Additional Uplinks. Physically, these are two PCI Express ports operating in PCIe x8 Gen3 and PCIe x16 Gen3 modes, both of them are 8.0 GT / S.

    For the interaction of the CPU and Intel C620 PCH, 3 buses are used: DMI and two PCI Express ports

    For the interaction of the CPU and Intel C620 PCH, 3 buses are used: DMI and two PCI Express ports

    . Why did you need to reconsider the existing communication topology with the Intel C620? First, up to 4x 10GbE network controllers with RDMA functionality can be integrated with PCH. Secondly, a new and faster generation of Intel QuickAssist Technology (QAT) coprocessors is responsible for encrypting network traffic and exchanging with the storage subsystem, providing hardware support for compression and encryption. And finally, the "engine of innovation" - Innovation Enginewhich will be available only to OEMs.

    Scalability and flexibility


    An important property is the ability to optionally select not only the PCH connection topology, but also the priorities of the internal resources of the chip in access to high-speed communication channels with the central processor (s). In addition, in the special EPO (EndPoint Only Mode) mode, PCH connection is carried out in the status of a regular PCI Express device containing 10 GbE and Intel QAT resources. At the same time, the classic DMI interface, as well as a number of Legacy subsystems shown in black on the diagram, are disabled.

    Internal architecture of Intel C620 PCH

    Internal architecture of Intel C620 PCH

    Theoretically, this makes it possible to use more than one Intel C620 PCH chip in the system, scaling the functionality of 10 GbE and Intel QAT in accordance with performance requirements. At the same time, Legacy functions that are needed only in a single copy can only be enabled on one of the installed PCH chips.

    So, the final word in the design will belong to the platform developer, acting on the basis of both technological and marketing factors in accordance with the positioning of each specific product.

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