Configuring Sublime Text 3 to work with VHDL files

Work with VHDL in Sublime Text 3

Sublime Text editor significantly saves time when working with vhdl and verilog files. For those who have not worked with editors like Sublime Text, Notepad ++, etc. I will describe the main useful functions of these editors:

  • multiple selection / editing of lines of code (pressing the middle mouse button or while holding down the Ctrl key)
  • setting labels (bookmarks) in the code helps to navigate in large files. (Ctrl + F2 or via the menu item Goto → Bookmarks)
  • the ability to split the workspace into several windows (Alt + Shift + 2 or from the menu View → Layout)
  • opening one file several times (File -> New View into File)
  • commenting out selected lines of code (Ctrl + /)
  • search and replace (Ctrl + h)
  • search all open files (Ctrl + Shift + f)
  • insert snippets (code templates) (write a keyword + Tab key)
  • writing and using python functions
  • the ability to install various add-ons
  • flexible setting

Sublime Text Integration

First, we’ll dock the CAD software for working with FPGAs and the Sublime editor.

  • Integration of Sublime Text with Xilinx ISE:
    in ISE go to the menu Edit → Preferences → Editors: Text Editor → Editor = Custom
    Insert a line into the “Command line syntax” window:

    {C:\Program Files\Sublime Text 3\sublime_text.exe} $1
  • Integration of Sublime Text with Xilinx Vivado:
    Tools → Options → Text Editor → Current Editor: Sublime
    Tools → Options → Text Editor → Current Editor: Custom Editor
    Specify the path to the editor, for example:
    C:\Program Files\Sublime Text 3\sublime_text.exe [file name]


Various plugins (packages) extend the functionality of the editor. Packages can be
installed both online and offline.

To install plugins in offline mode, you need to do some simple manipulations:

  1. Download the required plugin from GitHub
  2. Extract from archive
  3. Rename the folder, for example, “Sublime-HDL-master” to “Sublime HDL”
  4. The resulting folders are copied to the Packages folder (the location of this folder is easy to find by choosing the menu item Preferences → Browse Packages in Sublime Text)

SyncViewScroll - a plugin for synchronizing vertical and horizontal scrolling when working in multiple windows. For the plugin to work, you need to select View → Sync Scroll in the menu for each window.

Text Pastry is a plugin for automatic multiple numbering. It helps a lot when working with a large number of numbered signals / ports.

How to work with Text Pastry
  1. Select the necessary sections of the lines
  2. Call the menu Ctrl + Shift + P
  3. We are looking for the item “Text Pasty Command Line”
  4. In the window that appears, located at the bottom of the screen, enter:
    • 0 - numbering from 0
    • \ i (1,10) - numbering from 1 with an increment of 10
    • 1 end = 4 - numbering 1, 2, 3, 4, 1, 2, 3, 4, etc.
    • letters ac upper - A, B, C, A, B, C, etc.
    • letters ac upper x3 - A, A, A, B, B, B, C, C, C, etc.
    • 1 x3 - 1, 1, 1, 2, 2, 2, 3, 3, 3, etc.
    • xyz - x, y, z, x, y, z, x, y, z, etc.

Sublime Verilog - syntax support for the Verilog language

Verilog Gadget - a set of functions and snippets for working with Verilog files.

SmartVHDL - VHDL syntax support. Also, when you hover over a signal or port in the code, a window appears with a hint about the type (number of bits) of this signal / port. When you hover over a signal, the “Goto Definishion” item will appear in the context menu - transition to the place of announcement of the signal.

VHDL Mode - a set of functions and snippets for working with VHDL files. The main part of the functions is launched, for example, by the keyboard shortcut Atl + K, C, P, where C and P are pressed alternately. Main functions:

  • Copy port data (port names, data types)
  • Insert port data as signal declaration
  • Insert port data as component declaration
  • Testbench generation based on copied port data
  • Code auto-formatting (tab alignment, etc.)

Ucf file support

By default, the Sublime editor cannot work with ucf files. Ucf markup is equivalent to tcl markup. It remains only to explain this to the editor:

  • Create a new Tcl.sublime-settings file in the Packages folder
  • Fill the file with a line
    {"extensions" : ["ucf"]}
  • Save file

Creating code templates (snippets)

Let us need to insert a code template:

My_proc : Process(clk, rst, data_in) 
  if(clk'event and clk = '1') then
    if(rst = '1') then    
    else then -- rst = 0
    end if; -- data_in
  end if;--clk
end process My_proc;

And we would like that after inserting the text by pressing Tab, the cursor should be positioned at My_proc, clk, rst, data_in, to quickly change the values ​​of this data. To do this, create a new snippet: Tools → Developer → New Snippet. Editing data:

process rst} : Process(${2:clk}, ${3:rst}, ${4:data_in}) 
  if($2'event and $2 = '1') then
    if($3 = '1') then    
    else then -- $3 = 0
    end if; -- $4
  end if;--$2
end process $1;

Save this snippet. Now, when writing the procrst keyword, our template will be inserted at the current cursor position.

Read more about creating templates in the article “How to create a snippet?” .

Writing custom functions in python

Details about creating functions (plugins) were described in the articles “How to write a simple plugin” , “How to write a complex plugin” .

Inserting snippets is, of course, good, but I would like, for example, for the same process creation template to be filled out automatically depending on the input signals, and also for the process to be modified in the presence of signals such as rst and ce. More usually, after the process, the external ports of the module are assigned the values ​​of the internal signals, albeit also done automatically.

To parse VHDL file data, we will use the functions of the Vhdl mode plugin.

An approximate algorithm of our actions:

  1. Get data on all module ports
  2. All ports of type “in” should be included in the process header.
  3. If there are ports called ce and / or rst, then add the corresponding if else conditions to the process
  4. After the process, insert lines for assigning output ports to the values ​​of internal signals (usually such signals are also called as the port, adding the prefix "s_" or "_net")

First, create a new snippet:

procclksource.vhdlprocess clk

Here $ {DATAINPORTS} is the label where the process description will be inserted,
$ {OUTPORTS} is the label where internal output signals will be assigned to the external output ports.

Save it under the name, for example, test.sublime-snippet in the VHDL Mode / Snippets folder.
We will use the written functions in the VHDL Mode folder. Since I have initial knowledge of python, we will modify the functions of the plugin, by analogy with those already described in it.

In the file, create new functions in the Interface () class, call them in_port and out_port:

def in_port(self):
  Generate Process depending on the input ports
  lines = []
  bus_index = ""       
  max_data = ""
  my_ports = ""
  is_clk = False
  is_ce = False
  is_rst = False
  if self.if_ports:            
      for port in self.if_ports:            
          if port.mode.lower() == 'in':
              if == ('clk'):                       
                  is_clk = True
                  my_ports =                        
                  if == ('ce'):
                      is_ce = True                           
                  elif == ('rst'):
                      is_rst = True                                                   
                  my_ports = my_ports + ", " +                
      lines.append("Process("+ my_ports +')' )
      if is_clk:            
          lines.append("  if(clk'event and clk = '1') then")
          if is_rst and is_ce:
              lines.append("if(rst = '1') then")
              lines.append("elsif (ce = '1') then")
              lines.append("end if; -- rst")
          elif is_rst:
              lines.append("if(rst = '1') then")
              lines.append("else -- working body ")
              lines.append("end if; -- rst")
          elif is_ce:
              lines.append("if (ce = '1') then")
              lines.append("end if; -- 
          lines.append("  end if;--clk")
      lines.append("end process;")
      # lines.append(str(testind
      indent_vhdl(lines, 1)
      return '\n'.join(lines)
      return None
def out_port(self):
  Generate data after Process
  lines = []
  if self.if_ports:            
      for port in self.if_ports:            
          if port.mode.lower() == 'out':
              lines.append("{} <= {}_net;".format(,
      indent_vhdl(lines, 1)
      return '\n'.join(lines)
      return None 

The out_port function inserts the lines behind the process, for example:
data_out1 <= data_out1_net;
data_out2 <= data_out2_net;

Create a new file in the VHDL Mode folder, call it, insert the text:
import sublime
import sublime_plugin
from.import vhdl_interface as face
class PasteAsProcess(sublime_plugin.TextCommand):
    def run(self, edit):
        snippet_clk = "Packages/VHDL Mode/Snippets/test.sublime-snippet"
        in_port_str = face._interface.in_port()
        out_port_str = face._interface.out_port()
              "name"     : snippet_clk,
              "DATAINPORTS" : in_port_str,
              "OUTPORTS" : out_port_str

It remains to assign hot keys. Since our class is called PasteAsProcess, the command should be called paste_as_process (before the characters, except for the first one, written in upper case, you must put a underscore).

Go Preferences → Key Bildings. Insert the line:

{"keys": ["alt+k", "p", "z"], "command": "paste_as_process",    "context": [{"key": "selector", "operand": "source.vhdl"}] },

Now, to work, we first need to copy the values ​​of the vhdl ports of the file with the key combination “alt + k”, “p”, “w” (by default). Then call our function with the keys “alt + k”, “p”, “z”.


Snippets and functions greatly simplify working with vhdl files.

Even an initial knowledge of python is enough to write simple but working functions.

PS: I’ll leave a link to the folder with my settings. To work, you need to replace the Sublime Text 3 folder at: C: \ Users \ User \ AppData \ Roaming \

My snippets:

  • sint (Signal integer), sstd, svector - signal description templates of the corresponding type
  • ibuf, ibufds etc. - description of buffers
  • generichelp - hint example how to apply generic correctly
  • teststd, testvector, etc. - processes for testbench with appropriate data types
  • procclk, procce, procrst - processes with signals clk, ce, rst
  • clk, net, inst - templates for ucf files

My functions:

  • Binding Alt + K, C, P (Copy Ports), Alt + K, P, Z - pasting the process described in this article
  • Binding Alt + K, C, P (Copy Ports), Alt + K, P, T (Paste Testbench) - redid the function of the VHDL MODE plugin, now test processes for all input signals are generated

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