August 26, 2014 at 07:53Command sets should be free: arguments for RISC-V
- Transfer
Note by the translator. In the original article, the authors (one of them is the pioneer of RISC processors D. Patterson) argue the need to develop open ISAs (instruction set architecture, processor instruction sets) and products based on them. The arguments put forward are the stimulation of the development of those areas of computer technology and economic niches in which commercial companies are not interested or are not flexible enough. They are reminiscent of the success of open standards and free software.
I came across an extended version of this article (as well as a counter article from ARM representatives and a counter counter paragraph from the authors!) In the August issue of the Microprocessor Report (MPR). Access to MPR is limited and applies only to subscribers, but there is an open report in the public domain available on the website of the University of Berkeley. I offer his translation further.
Instruction Sets Should Be Free: The Case For RISC-V by Krste Asanović and David A. Patterson. EECS Department, University of California, Berkeley - Technical Report No. UCB / EECS-2014-146 www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.html
Custom systems on a chip (SoC), in which processors and their caches occupy only a small part of the chip, are becoming ubiquitous; Today it is already difficult to find an electronic device that does not use a processor as part of SoC. Thus, more and more companies are designing chips that include processors than before. Given the revolution made by open standards and open source software — for example, the TCP / IP network protocol and the Linux operating system — why does one of the most important interfaces remain proprietary?
Of course, some processor instruction sets (ISA, instruction instruction architecture) may be proprietary for historical and commercial reasons. However, there is not a single solid technical basis for explaining the lack of free, open options.
Note that ISA is actually an interface specification, but not its implementation. There are three approaches to the implementation of a certain interface:
1. Private closed, similar to Apple iOS.
2. Licensed open source, like Wind River VxWorks.
3. Free and open, whose users can modify and share, as is done on Linux.
Proprietary ISAs allow you to work with the first two approaches in practice, but you need a free, open ISA to support all three approaches.
From this we conclude that the industry will only benefit from a viable freely available open ISA to the same extent that it was beneficially influenced by the development of free open source software. For example, this will create a truly free open market for processor designs.ISA's fad patents are currently hindering it.
This can lead to:
1. Innovation through competition in the free market for many designers, including open and closed ISA implementations.
2. The general open core designs, which will be expressed in reducing the time to market for products, reducing the cost of reuse, fewer errors due to the close attention of many people 3 , and in transparency, which, for example, will complicate the implementation of secret backdoors by government agencies.
3. Processors available for more devices, which will help develop the Internet of Things (IoT, Eng. Internet of Things), with a cost of about a dollar.
In order for any ISA to be accepted by the open-source community, we believe that it must have a successful history of commercial use. The first question is, what style of ISA demonstrates such a story? Over the past 30 years, history has not known a single successful stack architecture ( Translator's note: a strange statement, given the success of Java bytecode and .NET CLI - stack architectures ). In addition to the DSP (digital signal processing) application segment, VLIW also failed: Multiflow surfaced belly up, and Itanium, despite the billions of dollars in investments from HP and Intel, did not receive recognition. For decades, not a single new CISCISA is not gaining success. Surviving CISC architectures translate their complex instructions into simpler ISAs, which is very justified for executing a valuable legacy code base. The new ISA, by definition, will not have such a base, so the additional costs of equipment and power consumption required for broadcasting are difficult to justify: why not immediately use the simpler ISA? RISC -like load-store instruction sets have been known for at least 50 years, since the era of the CDC 6600 Seymur Crey. While 80x86 won PC wars, RISC dominates the tablets and phones of the post-PC era. In 2013, more than 10 billion ARMs were sold, compared with 0.3 billion x86. Repeating what we said in 1980 4 , we believe that RISC is the best choice for a free and open ISA.
Moreover, the new RISC ISA can be better than its predecessors, if its development takes into account their mistakes:
To meet the needs of the embedded solutions market, RISCs even provided a solution to the problem of code size: ARM Thumb and MIPS16 added 16-bit formats to make the code even shorter than that of 80x86. Thus, there is a generally accepted agreement on how overall a good RISC ISA should look.
There are already three free and open RISC ISA 5s :
Since it usually takes years to polish all the details, it took 11 years for OpenRISC to mature and 4 years for RISC-V, it would be more correct to start with an existing ISA rather than form a committee and start from scratch. All RISCs are similar, so any of them can be a good candidate.
Since ISAs can exist for decades, you must first extrapolate and describe the future landscape of information technology in order to understand what features may be important in order to facilitate the prioritization process. Most likely, three platforms will prevail: IoT - billions of cheap devices with IP addresses and Internet access; 2) personal mobile devices, such as modern phones and tablets; 3) data centers (Warehouse-Scale Computers, WSCs). You can have different ISAs for each type of platform, but life will be easier if it is the same everywhere. Such a picture of the future offers four key requirements for it.
1. The format of "basic ISA plus extensions" 7. To increase efficiency and reduce costs, SoC systems add their own application-specific accelerators. To do this, as well as to maintain a stable code base, a free open ISA should have: a) a small core of instructions that are known to compilers and the OS, b) standard but optional extensions for frequent private SoC adaptation scenarios for a specific application, c) space for completely new instruction codes for accelerators.
2. Compact encoding of commands. A smaller amount of code is desirable because of the sensitivity of the price of IoT applications to the amount of memory used.
3. Quadruple-precision (QP) calculations over floating point numbers in addition to double and single precision. Some applications running in data centers today process such large amounts of data that they already use software libraries for QP.
4. 128-bit addressing in addition to 32-bit and 64-bit. The memory limitations of IoT devices mean that 32-bit addressing will be relevant for a long time. 64-bit addresses are the de facto standard for all large systems. Although WSC industry does not require all the 2 128 bytes, it is quite likely that in a decade the number needed in excess of 2 64(16 exabytes), for addressing SSD storage. The limited size of the address space is one of those ISA errors that are difficult to fix 8 , it makes sense to plan large addresses now.
The following table summarizes the information about the three free open ISAs according to these four criteria, as well as the availability of support by compilers and ported OSs.
Our community should come together around a single ISA to verify that a free, open ISA can work in practice. Only RISC-V meets all four requirements. It is also 10 to 20 years younger than the rest of the RISC, so we had the opportunity to analyze and correct their errors, such as SPARC and OpenRISC transition delay slots. Therefore, the RISC-V command system is simple and straightforward (see tables 4 and 5 of the original article, as well as www.riscv.org ). In addition to the fact that other ISAs do not fulfill many requirements, there are questions about the 64-bit SPARC V9 being proprietary, and OpenRISC has lost momentum.
RISC-V still has a big boost. Table 1 lists the various groups designing RISC-V-based SoCs. Partly due to the use of the highly productive, open Chisel 9 hardware design system , the University of Berkeley already has 8 types of chips and new developments in the process. Table 2 shows that one 64-bit RISC-V core occupies half the area, consumes half of the power and at the same time works faster than a 32-bit ARM with a similar pipeline or the same manufacturing process. Although it is difficult to completely eliminate our bias in this matter, we believe that RISC-V is the best and safe choice for a free open RISC ISA. Therefore, we will conduct a series of workshops 10 To expand the RISC-V community and, inspired by the examples in Table 3, we plan to create a non-profit foundation for the task of certification of implementations, as well as to support and develop ISA.
Our arguments are even clearer for an open ISA than for an open OS, as ISAs change very slowly, while algorithmic innovations and new applications require a continuous evolution of the OS. Like TCP / IP, it is an interface standard that is easier to maintain and develop than an OS.
Open ISAs have been used before, but they have never become popular due to a lack of demand for them. The low price and power consumption of IoT, the desire to have an alternative to 80x86 for data centers, and the fact that processor cores are just a small but ubiquitous part of all SoCs are combined into a proposal that can satisfy the emerging demand. RISC-V is primarily aimed at SoC, with a basic set of never-changing commands, given the long life of RISC's ideas, with a slowly evolving subset of optional extensions, as well as unique instructions that will never be reused. Although the first bridgehead for RISC-V can be IoT or WSC, our goal is wider: just as Linux has become the standard OS for most computing devices, we imagine RISC-V as the standard ISA for all computing devices of the future.
1. Letter from MIPS (2002). brej.org/yellow_star/letter.pdf .
2. Demerjian, C. (2013). “A long look at how ARM licenses chips: Part 1 of 2,” semiaccurate.com/2013/08/07/a-long-look-at-how-arm-licenses-chips
3. Raymond, E. (1999) . The Cathedral and the Bazaar. Knowledge, Technology & Policy, 12 (3), 23-49 // Per. Russian: Eric S. Raymond. Cathedral and Bazaar. lib.ru/LINUXGUIDE/bazar.txt
4. Patterson, D. & D. Ditzel. (1980) “The Case for the Reduced Instruction Set Computer.” SIGARCH Computer Architecture News 8.6, 25-33.
5. We recently learned about the intentions of the Open Core Foundation to design a 64-bit open core based on SH-4 by 2016.
6. Waterman, A. et al. (2014). The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0. EECS Technical Report No. UCB / EECS-2014-54, UC Berkeley.
7. Estrin, G. (1960) “Organization of computer systems: the fixed plus variable structure computer.” Western Joint IREAIEE-ACM Computer Conference, 33-40.
8. Bell, G., & W. Strecker. (1976) Computer structures: What have we learned from the PDP-11 ?, 3rd ISCA, 1-14.
9. Bachrach, J., et al. (2012) “Chisel: constructing hardware in a Scalaembedded language.” Proc. 49th DAC, 1216-1225.
10. The first RISC-V workshop will be held January 14-15, 2015 in Monterey, CA. www.regonline.com/riscvworkshop
Table 1. RISC-V projects outside the University of Berkeley (for the full table, see the original report).
Table 2. Comparison of 32-bit ARM (Cortex A5) with 64-bit RISC-V core (Rocket), performed on one technical process (TSMC 40GPLUS). Data taken from the ARM site and from an article by Y. Lee et al. “A 45nm 1.3GHz 16.7 Double-Precision GFLOPS / W RISC-V Processor with Vector Accelerators”, which will be published in the proceedings: the 40th European Solid-State Circuits Conference, September 22-24, 2014:
Table 3. Examples of open-source software funds that have supported and developed open-source projects for decades:
Tables 4 and 5. RISC-V instruction set format. See in the original report.
I came across an extended version of this article (as well as a counter article from ARM representatives and a counter counter paragraph from the authors!) In the August issue of the Microprocessor Report (MPR). Access to MPR is limited and applies only to subscribers, but there is an open report in the public domain available on the website of the University of Berkeley. I offer his translation further.
Instruction Sets Should Be Free: The Case For RISC-V by Krste Asanović and David A. Patterson. EECS Department, University of California, Berkeley - Technical Report No. UCB / EECS-2014-146 www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.html
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Translation is done with the kind permission of the authors.
Copyright © 2014, by the author (s).
All rights reserved.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page . To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission.
The opinion of the authors may not coincide with the opinion of the translator. I will also be grateful for any inaccuracies noted in the translation, and clarification of its contents.
Copyright © 2014, by the author (s).
All rights reserved.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page . To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission.
The opinion of the authors may not coincide with the opinion of the translator. I will also be grateful for any inaccuracies noted in the translation, and clarification of its contents.
Custom systems on a chip (SoC), in which processors and their caches occupy only a small part of the chip, are becoming ubiquitous; Today it is already difficult to find an electronic device that does not use a processor as part of SoC. Thus, more and more companies are designing chips that include processors than before. Given the revolution made by open standards and open source software — for example, the TCP / IP network protocol and the Linux operating system — why does one of the most important interfaces remain proprietary?
Arguments for Free, Open ISA Support
Of course, some processor instruction sets (ISA, instruction instruction architecture) may be proprietary for historical and commercial reasons. However, there is not a single solid technical basis for explaining the lack of free, open options.
- This is not a mistake or omission. Companies that own successful ISAs such as ARM, IBM, and Intel hold patents for the quirks of their team systems, which prevents others from using them without a license 1 . Negotiations on the use last for 6-24 months and can cost from 1 to 10 million dollars, which excludes from the process academic organizations and everyone who needs only small volumes of production 2 . The license from ARM does not even allow you to design your own kernel; you only get the right to use themdesign (only about 15 large companies are eligible to create new ARM cores). Even OpenPOWER is an oxymoron; You must pay IBM to use this ISA. Reasonable business, this licensing practice stifles competition and innovation by prohibiting many from designing and sharing their own ISA-compliant kernels.
- This is not because ISA owners themselves produce the vast majority of the software for their systems. Despite the size of software ecosystems that have grown around the popular ISA, the lion's share of the software for them is written by outside people.
- These companies do not have the sacred knowledge required to create an adequate ISA. This is a lot of work, but many today can design a set of instructions.
- The most popular ISAs are not the most elegant. Both 80x86 and ARM are not considered standards of good design.
- Verification of compatibility with ISA does not require company control. Open organizations developed mechanisms for certifying hardware compatibility many years ago. Examples: IEEE 754 standard for floating point numbers, Ethernet, PCIe. If this were not so, open IT standards would not be so popular.
- Finally, there is no guarantee that proprietary ISAs will last long. If a company goes broke and disappears, it takes its ISA with it. The demise of DEC has completed the development of Alpha and VAX instruction sets.
Note that ISA is actually an interface specification, but not its implementation. There are three approaches to the implementation of a certain interface:
1. Private closed, similar to Apple iOS.
2. Licensed open source, like Wind River VxWorks.
3. Free and open, whose users can modify and share, as is done on Linux.
Proprietary ISAs allow you to work with the first two approaches in practice, but you need a free, open ISA to support all three approaches.
From this we conclude that the industry will only benefit from a viable freely available open ISA to the same extent that it was beneficially influenced by the development of free open source software. For example, this will create a truly free open market for processor designs.ISA's fad patents are currently hindering it.
This can lead to:
1. Innovation through competition in the free market for many designers, including open and closed ISA implementations.
2. The general open core designs, which will be expressed in reducing the time to market for products, reducing the cost of reuse, fewer errors due to the close attention of many people 3 , and in transparency, which, for example, will complicate the implementation of secret backdoors by government agencies.
3. Processors available for more devices, which will help develop the Internet of Things (IoT, Eng. Internet of Things), with a cost of about a dollar.
Arguments in support of RISC as a style for a free, open ISA
In order for any ISA to be accepted by the open-source community, we believe that it must have a successful history of commercial use. The first question is, what style of ISA demonstrates such a story? Over the past 30 years, history has not known a single successful stack architecture ( Translator's note: a strange statement, given the success of Java bytecode and .NET CLI - stack architectures ). In addition to the DSP (digital signal processing) application segment, VLIW also failed: Multiflow surfaced belly up, and Itanium, despite the billions of dollars in investments from HP and Intel, did not receive recognition. For decades, not a single new CISCISA is not gaining success. Surviving CISC architectures translate their complex instructions into simpler ISAs, which is very justified for executing a valuable legacy code base. The new ISA, by definition, will not have such a base, so the additional costs of equipment and power consumption required for broadcasting are difficult to justify: why not immediately use the simpler ISA? RISC -like load-store instruction sets have been known for at least 50 years, since the era of the CDC 6600 Seymur Crey. While 80x86 won PC wars, RISC dominates the tablets and phones of the post-PC era. In 2013, more than 10 billion ARMs were sold, compared with 0.3 billion x86. Repeating what we said in 1980 4 , we believe that RISC is the best choice for a free and open ISA.
Moreover, the new RISC ISA can be better than its predecessors, if its development takes into account their mistakes:
- The exception is too much: the lack of load / store commands for bytes and half-words in the first version of Alpha ISA and the absence of load / store for floating-point numbers in MIPS I.
- Inclusion of redundancy: built-in shift in ARM instructions and SPARC register windows.
- Influence of microarchitectural details on ISA: delayed transitions in MIPS and SPARC, trap barriers for floating-point numbers on Alpha.
To meet the needs of the embedded solutions market, RISCs even provided a solution to the problem of code size: ARM Thumb and MIPS16 added 16-bit formats to make the code even shorter than that of 80x86. Thus, there is a generally accepted agreement on how overall a good RISC ISA should look.
Arguments for using the existing free open RISC ISA
There are already three free and open RISC ISA 5s :
- SPARC V8 - To the credit of Sun Microsystems, it made SPARC V8 the IEEE standard in 1994.
- OpenRISC is a GNU-licensed open-source project, launched in 2000, with a 64-bit ISA completed in 2011.
- RISC-V - in 2010, partly due to ARM restrictions on its IP and due to the lack of 64-bit modes, as well as due to the general grotesque nature of ARM v7, we and our students Andrew Waterman and Yunsup Lee developed RISC-V 6 (pronounced “RISC-5”) for the needs of our research and teaching activities and released under the BSD license.
Since it usually takes years to polish all the details, it took 11 years for OpenRISC to mature and 4 years for RISC-V, it would be more correct to start with an existing ISA rather than form a committee and start from scratch. All RISCs are similar, so any of them can be a good candidate.
Since ISAs can exist for decades, you must first extrapolate and describe the future landscape of information technology in order to understand what features may be important in order to facilitate the prioritization process. Most likely, three platforms will prevail: IoT - billions of cheap devices with IP addresses and Internet access; 2) personal mobile devices, such as modern phones and tablets; 3) data centers (Warehouse-Scale Computers, WSCs). You can have different ISAs for each type of platform, but life will be easier if it is the same everywhere. Such a picture of the future offers four key requirements for it.
1. The format of "basic ISA plus extensions" 7. To increase efficiency and reduce costs, SoC systems add their own application-specific accelerators. To do this, as well as to maintain a stable code base, a free open ISA should have: a) a small core of instructions that are known to compilers and the OS, b) standard but optional extensions for frequent private SoC adaptation scenarios for a specific application, c) space for completely new instruction codes for accelerators.
2. Compact encoding of commands. A smaller amount of code is desirable because of the sensitivity of the price of IoT applications to the amount of memory used.
3. Quadruple-precision (QP) calculations over floating point numbers in addition to double and single precision. Some applications running in data centers today process such large amounts of data that they already use software libraries for QP.
4. 128-bit addressing in addition to 32-bit and 64-bit. The memory limitations of IoT devices mean that 32-bit addressing will be relevant for a long time. 64-bit addresses are the de facto standard for all large systems. Although WSC industry does not require all the 2 128 bytes, it is quite likely that in a decade the number needed in excess of 2 64(16 exabytes), for addressing SSD storage. The limited size of the address space is one of those ISA errors that are difficult to fix 8 , it makes sense to plan large addresses now.
The following table summarizes the information about the three free open ISAs according to these four criteria, as well as the availability of support by compilers and ported OSs.
Arguments for RISC-V as a Free, Open ISA
Our community should come together around a single ISA to verify that a free, open ISA can work in practice. Only RISC-V meets all four requirements. It is also 10 to 20 years younger than the rest of the RISC, so we had the opportunity to analyze and correct their errors, such as SPARC and OpenRISC transition delay slots. Therefore, the RISC-V command system is simple and straightforward (see tables 4 and 5 of the original article, as well as www.riscv.org ). In addition to the fact that other ISAs do not fulfill many requirements, there are questions about the 64-bit SPARC V9 being proprietary, and OpenRISC has lost momentum.
RISC-V still has a big boost. Table 1 lists the various groups designing RISC-V-based SoCs. Partly due to the use of the highly productive, open Chisel 9 hardware design system , the University of Berkeley already has 8 types of chips and new developments in the process. Table 2 shows that one 64-bit RISC-V core occupies half the area, consumes half of the power and at the same time works faster than a 32-bit ARM with a similar pipeline or the same manufacturing process. Although it is difficult to completely eliminate our bias in this matter, we believe that RISC-V is the best and safe choice for a free open RISC ISA. Therefore, we will conduct a series of workshops 10 To expand the RISC-V community and, inspired by the examples in Table 3, we plan to create a non-profit foundation for the task of certification of implementations, as well as to support and develop ISA.
Conclusion
Our arguments are even clearer for an open ISA than for an open OS, as ISAs change very slowly, while algorithmic innovations and new applications require a continuous evolution of the OS. Like TCP / IP, it is an interface standard that is easier to maintain and develop than an OS.
Open ISAs have been used before, but they have never become popular due to a lack of demand for them. The low price and power consumption of IoT, the desire to have an alternative to 80x86 for data centers, and the fact that processor cores are just a small but ubiquitous part of all SoCs are combined into a proposal that can satisfy the emerging demand. RISC-V is primarily aimed at SoC, with a basic set of never-changing commands, given the long life of RISC's ideas, with a slowly evolving subset of optional extensions, as well as unique instructions that will never be reused. Although the first bridgehead for RISC-V can be IoT or WSC, our goal is wider: just as Linux has become the standard OS for most computing devices, we imagine RISC-V as the standard ISA for all computing devices of the future.
Literature
1. Letter from MIPS (2002). brej.org/yellow_star/letter.pdf .
2. Demerjian, C. (2013). “A long look at how ARM licenses chips: Part 1 of 2,” semiaccurate.com/2013/08/07/a-long-look-at-how-arm-licenses-chips
3. Raymond, E. (1999) . The Cathedral and the Bazaar. Knowledge, Technology & Policy, 12 (3), 23-49 // Per. Russian: Eric S. Raymond. Cathedral and Bazaar. lib.ru/LINUXGUIDE/bazar.txt
4. Patterson, D. & D. Ditzel. (1980) “The Case for the Reduced Instruction Set Computer.” SIGARCH Computer Architecture News 8.6, 25-33.
5. We recently learned about the intentions of the Open Core Foundation to design a 64-bit open core based on SH-4 by 2016.
6. Waterman, A. et al. (2014). The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0. EECS Technical Report No. UCB / EECS-2014-54, UC Berkeley.
7. Estrin, G. (1960) “Organization of computer systems: the fixed plus variable structure computer.” Western Joint IREAIEE-ACM Computer Conference, 33-40.
8. Bell, G., & W. Strecker. (1976) Computer structures: What have we learned from the PDP-11 ?, 3rd ISCA, 1-14.
9. Bachrach, J., et al. (2012) “Chisel: constructing hardware in a Scalaembedded language.” Proc. 49th DAC, 1216-1225.
10. The first RISC-V workshop will be held January 14-15, 2015 in Monterey, CA. www.regonline.com/riscvworkshop
Table 1. RISC-V projects outside the University of Berkeley (for the full table, see the original report).
Table 2. Comparison of 32-bit ARM (Cortex A5) with 64-bit RISC-V core (Rocket), performed on one technical process (TSMC 40GPLUS). Data taken from the ARM site and from an article by Y. Lee et al. “A 45nm 1.3GHz 16.7 Double-Precision GFLOPS / W RISC-V Processor with Vector Accelerators”, which will be published in the proceedings: the 40th European Solid-State Circuits Conference, September 22-24, 2014:
Table 3. Examples of open-source software funds that have supported and developed open-source projects for decades:
Tables 4 and 5. RISC-V instruction set format. See in the original report.