Itanium Poulson: what's new


    In early 2011, Intel announced the upcoming release of the Itanium generation stone, code-named “Poulson” at the Solid State Circuit, and most recently, Intel revealed the first details of this processor during the HotChips conference held at Stanford University.

    Observing the development of the Itanium line may also be interesting for those who use Intel Xeon-based solutions, as many developments are transferred from Itanium to new versions of Xeons (such as QuickPath and Scalable Memory Interconnects, Intel 7500 Scalable Memory Buffer and the use of DDR3 )

    The key features of the processor are as follows: the new architecture, twice as many processor cores, twice as many process processing capabilities.

    The new chip will carry eight processor cores on a substrate and be manufactured using a 32-nm process technology, which will ultimately produce 3.1 billion transistors on the CPU area (for comparison, there are about a billion semiconductors in the second-generation Core i7).

    A closer look at the new processor reveals the following features, which generally fall under the direction of RAS: Reliability (Availability), Availability (Availability) and Serviceability (ability).

    1. Increased fault tolerance of the processor due to the technology of repeated execution of commands "Instruction Replay", based on the new architecture of the command pipeline. HP wrote about it in the blog on Habréalso interested in improving fault tolerance technology. The new Itanium will be the first processor to use this technology.

    The changes will affect almost all the basic structures in the architecture of Poulson: LLC, MLI, MLD, IEU, FPU.

    2. An advanced instruction buffer implements the multithreading capabilities of Hyper-Threading, supporting the execution of instruction flows in two domains. The EPIC architecture used in IA64-based processors has always had enhanced parallelization support, and in Poulson this integration will be even more powerful by supporting Dual Domain Multithreading, which processes two instruction streams separately.

    The main innovations of multithreading will be as follows: dual threaded register files, dual threaded data side Translation buffers (TLB).

    3. New processor instructions: commands for working with integers (mpy4, mpyshl4, clz); teams on parallelization and multithreading technologies Data Access Hints (mov dahr), Expanded Software Prefetch (ifetch.count) and Thread Control (hint @ priority). All of these innovations serve one purpose - to enable Itanium architecture to grow naturally through future enhancements.

    The new Itanium has 54 MB of memory (50 MB SRAM), and the improved work of QPI and SMI will bring a 33% increase in system performance.

    As you can see, most of the changes are connected precisely with the desire to get the full return from 8 cores and the ability to execute up to 12 instructions per cycle, due to the maximum number of parallel (and architectural - and perpendicular co) processes. Despite the increased power, Intel engineers were able to achieve reduced CPU power consumption.

    In parallel with the development of Poulson, Intel is busy with another Itanium chip - Kittson. which will be presented officially later. Both new processors will be fully compatible with the modern Itanium 9300 series (Tukwila) in program code, so owners of solutions released on the basis of these processors released in the past will be able to upgrade without any problems for running applications.

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