UDB. What is it? Part 8. Addressing UDB
We conclude our epic with the translation of Cypress proprietary documentation about UDB. The latest issue - about addressing UDB - is in front of you.
The general content of the cycle “UDB. What is it?"
Part 1. Introduction. Pld.
Part 2. Datapath.
Part 3. Datapath FIFO.
Part 4. Datapath ALU.
Part 5. Datapath. Useful little things.
Part 6. Management and status module.
Part 7. Timing and reset control module.
Part 8. UDB addressing. (Current article)
21.3.5 UDB Addressing
The UDB pair has three unique address spaces:
- 8-bit working registers - a bus controller that has access to only 8 bits of data per bus cycle can use this address space to read or write any UDB working registers. These include the registers with which the CPU and DMA interact during normal operation.
- 16-bit work registers - A 16-bit bus controller, such as a DMA or PSoC 5LP Cortex-M3, can access 16 bits in one bus cycle to enable data transfer to functions that require 16 bits or more. Despite the fact that this address space is not tied to the area to which the 8-bit space is tied, it has access to the same registers, only to a pair at a time.
- 8- or 16-bit configuration registers - these registers configure UDB to execute a function. After configuration, the registers are usually set to a static state during UDB operation. These registers retain their state after sleep mode.
Everything is somehow complicated. In my opinion, for the first two points it is easier to introduce the concept of addressing methods with different bit depths of the working register. Through 8-bit and through 16-bit working registers respectively. If you are confused when reading these paragraphs, try to consider the text in this way. Different windows in the address space of the CPU, providing addressing of the same through the working registers of different bits. That's all.
22.214.171.124 Working Register Address Space
Work registers are used during normal operation and include batteries, data registers, FIFOs, control and status registers, a mask superimposing register, and an auxiliary control register.
Figure 21-43 shows a register map of one UDB.
On the right in Figure 21-43 is a 16-bit address that is always even. In this case, the UDB number has a dimension of 5 bits, not 4, due to the even location of the addresses. The high 4 bits still set the register number.
Figure 21-43. Working registers UDB.
8-bit working register access
In this mode, access to all UDB registers is via addresses aligned on the byte boundary. In access mode for 8-bit registers, as shown in Figure 21-44, all data bytes written to UDB are aligned with the low byte of the 16-bit UDB bus.
In this mode, access at any time can only be accessed to one byte.
Figure 21-44. Access to 8-bit working register.
16-Bit Working Register Address Space
A 16-bit address space designed for efficient DMA access and providing programmatic CPU access in processors that support it, such as the Cortex-M3 in PSoC 5LP. There are two modes of access to 16-bit registers: the default mode and the concatenation mode. As shown in Figure 21-45, in default mode it accesses the specified register in UDB 'i' through the low byte and to the same register in UDB 'i + 1' through the high byte. This makes processing 16-bit data efficient in neighboring UDBs (in order of addresses) configured as 16-bit functions.
Figure 21-45. Access to 16-bit working registers in default mode.
In concatenation mode, the registers of one UDB are combined to form 16-bit registers, as shown in Figure 21-46. In this mode, the 16-bit data bus of the UDB array must access a pair of registers in the UDB in the format shown in the figure. For example, when accessing the register A0, access to A0 through the low byte and to A1 through the high byte will actually occur.
Figure 21-46. Access to a 16-bit working register in concatenation mode.
The use of DMA is limited by the capacity of the 16-bit working register. It is not enough when working with functions greater than 16 bits. This is caused by address overlays, as shown in
Tables 21-25. Optimized address space for 16-bit UDB functions.
|Address||High byte is written to||Low byte is written to|
When the DMA transmits 16 bits to address 0, the low and high bytes are written to UDB0 and UDB1, respectively. In the next 16-bit DMA transmission to address 2, the value in UDB1 is overwritten by the low byte of this transmission.
To prevent problems associated with such memory organization, it is recommended for functions whose bit depth is more than 16 bits to start the DMA process for an area with 8-bit working registers.
126.96.36.199 Configuration Register Address Space
Configuration is done at the UDB pair level. A UDB pair consists of two UDBs and an associated tracer channel, as shown in Figure 21-47.
Figure 21-47. Address scheme for configuring a UDB pair.
188.8.131.52 UDB Configuration Address Space
Figure 21-48 shows the address configuration diagram of a specific UDB. As you can see, this configuration space is duplicated on both UDBs in pairs. In total, 128 bytes (7 bit addresses) are reserved for each UDB configuration, which are divided into 16-bit segments. It is worth noting that 16-bit access to odd borders is not supported. Reading always returns 16 bits in the configuration space, and unnecessary bytes can be ignored.
Figure 21-48. The address space of the UDB configuration.
184.108.40.206 Routing Configuration Address Space
The UDB trace configuration consists of embedded RAM bits to control the status of gateway switches, segmentation, and input / output buffers.
21.3.6 System Bus Access Coherency
UDB registers have dual access mode:
- access to the system bus, in which the CPU or DMA reads or writes to the UDB register;
- UDB internal access, in which the UDB function updates or uses the contents of the register
220.127.116.11 Simultaneous System Bus Access
The table below contains a list of possible concurrent access events and the required behavior.
Table 21-26. Simultaneous access to the system bus.
|Register||Write from UDB |
Write from bus
|Write from UDB |
Read from bus
|Read from UDB |
Write from bus
|Read from UDB |
Read from Bus
|Ax||Uncertain Result||Not available directly a, b||UDB reads the previous value||The bus and UDB read the current value.|
|Fx||Not supported (UDB and bus must have multidirectional access)||If FIFO status flags are used, simultaneous read / write||Not supported (UDB and buses must have multidirectional access)|
|ST||Not available, bus not writing||The bus reads the previous value.||Not available, UDB does not read|
|CTL||Not available, UDB does not write||UDB reads the previous value||The bus and UDB read the current value.|
|CNT||Uncertain Result||Not available directly from|
|ACTL||Not available, UDB does not write|
|MC (RO)||Not available, bus not writing||Not available directly d||Not available, bus not writing|
a. Ax registers can be safely read using the FIFO software capture function.
b. In Dx registers, FIFOs can only be dynamically written. In this mode, direct reading of Dx registers is not available.
c. The CNT register can only be read safely when it is disabled. An alternative for dynamically reading the CNT value is tracing the output to the SC register (in transparent mode).
d. MC register bits can be traced to the status register inputs (in transparent mode) for safe reading.
18.104.22.168 Coherent Accumulator Access (Atomic Reads and Writes)
UDB batteries are the primary goal of data processing. Therefore, reading these registers directly during normal operation gives an undefined result, as shown in the table above. However, there is built-in support for atomic readings in the form of program capture implemented on blocks connected in a chain. In such a usage model, reading the last significant battery transfers data from all the blocks connected in the chain to the associated FIFOs. Atomic recording in FIFO can be implemented programmatically. Individual write operations can be performed at the FIFO input, and then the FIFO status signal to which the last recording was made can be forwarded to all linked blocks, while the FIFO data will be transferred to the Dx or Ax registers.
Afterword from the translator
This translation cycle was made as a response to the commentary on the article , where it was proposed first to briefly describe what UDB is. Now it is clear that for a brief answer it would be necessary to quote at least half of the materials presented here, otherwise the answer would still be incomplete. But now all the materials are translated and compiled. Mission accomplished.
While the work was going on, we also drew attention to another interesting PSoC block, which is poorly known to anyone, but is fraught with tremendous power. This is DFB, Digital Filter Block. True, it’s scary to rush into the translation. From the translation about UDB it is clear that one documentation is not enough, oh, practice is needed. The trouble is that there are few ready-made examples on UDB, but they are. It has not yet been possible to find something worthwhile from the examples on DFB (Cypress itself made a digital filter in the form of a black box, it works, but it’s not clear how). Translation without examples will not make sense. Therefore, taking this opportunity, we draw the attention of readers to this block. Perhaps someone in the comments will provide links to good examples. If we manage to deal with this block, it will be possible to make a cycle of translations and practical articles on it. In the meantime, that’s all.