March 16, 2019 at 16:12The new standard on the basis of PCIe 5.0 will “connect” the CPU and GPU - what is known about it
The CXL Consortium has introduced a new open standard - Compute Express Link ( CXL ). It will help to organize high-speed communication between the processor and other devices - GPU, FPGA and memory. CXL 1.0 is based on the PCIe 5.0 interface, which is expected to be specification this year . Let's talk about the technical details and analogues of the solution. / Wikimedia / CINECA / CC BY
The need for processing and encryption of large volumes of data, the development of AI systems and MO algorithms have led to an increase in the popularity of heterogeneous solutions. In them, general-purpose processors work together with accelerators - graphics processors, FPGAs and ASIC chips. Each component specializes in a specific task, which improves system performance.
When processing large amounts of data (for example, in data centers), channels for exchanging information between heterogeneous components sometimes become a “bottleneck”. To minimize delays , the CXL consortium (which includes cloud providers and data center equipment developers) introduced the Compute Express Link standard.
It is based on the PCI Express 5.0 interface, designed to connect server components. This means that the standard will support bandwidth between computing elements up to 128 GB / s on 16 lines. In this case, economical 128b / 130b encoding, implemented in PCI Express 3.0, will be used .
Schematically, the connection can be represented as follows:
CXL has three interface methods. The first is the I / O mode for transmitting commands and updating device statuses. The second is the memory protocol for sharing RAM between the host and accelerator. The third is an interface that will ensure memory coherence.
The PCIe 5.0 bus is specially designed to solve problems that require maximum throughput - working with graphics processors, network technologies, and highly loaded systems. Therefore, CXL developers expect the new standard to be in demand among machine learning institutes and data center operators. Since the technology is “ sharpened ” for GPU, FPGA, ASIC and other accelerators, it will most likely not be used in the architecture of user PCs.
The IT community is of the opinion that the new standard may not be widely adopted. Since the industry is already enoughsimilar standards and specifications, for example CCIX and GenZ (we will talk about them below). A wide adaptation of the standard may be hindered by the model of its distribution. Although Compute Express Link is an open standard, only members of the consortium have access to its full specification . And while it is not clear whether they will compete with each other in the market after the release.
/ Wikimedia / BiomedNMR / CC BY-SA
As we mentioned above, CXL has several analogues, including GenZ and CCIX.
The GenZ bus specification, called the "possible successor to PCIe," was released in February 2018. About fifty large IT companies took part in its development. The purpose of creating the standard does not differ from the goals of CXL - to increase the speed of data exchange between the processor, memory and graphics cards.
Representatives of the consortium argue that Gen-Z bypasses the point-to-point communication limitation that is present in PCIe and accesses memory directly. The specification is already ready and is in the public domain on the consortium website.
CCIX is another consortium of whicheminent corporations are listed . The first specification of the standard of the same name was released in the summer of 2018. It is based on PCIe 4.0, which allows achieving a throughput of 25 GB / s.
The architecture concept based on the first CCIX specification was already implemented by Xilinx on its Versal FPGA chip . In the near future, other market players also plan to introduce CCIX, some of them have already submitted test implementations.
At least two consortiums are already ahead of CXL in spec development speed. However, there is a chance that the advantages of the PCIe 5.0 standard will help CXL get ahead of the competition and become the industry standard for manufacturers of processors and heterogeneous systems. Devices based on this technology will help to speed up work with data in the data center and the cloud, and will find application in the development of AI systems and HPC solutions.
Why did you need a new standard
The need for processing and encryption of large volumes of data, the development of AI systems and MO algorithms have led to an increase in the popularity of heterogeneous solutions. In them, general-purpose processors work together with accelerators - graphics processors, FPGAs and ASIC chips. Each component specializes in a specific task, which improves system performance.
When processing large amounts of data (for example, in data centers), channels for exchanging information between heterogeneous components sometimes become a “bottleneck”. To minimize delays , the CXL consortium (which includes cloud providers and data center equipment developers) introduced the Compute Express Link standard.
What is known about the standard
It is based on the PCI Express 5.0 interface, designed to connect server components. This means that the standard will support bandwidth between computing elements up to 128 GB / s on 16 lines. In this case, economical 128b / 130b encoding, implemented in PCI Express 3.0, will be used .
Schematically, the connection can be represented as follows:
CXL has three interface methods. The first is the I / O mode for transmitting commands and updating device statuses. The second is the memory protocol for sharing RAM between the host and accelerator. The third is an interface that will ensure memory coherence.
What we write about in a corporate blog:
Potential and disadvantages
The PCIe 5.0 bus is specially designed to solve problems that require maximum throughput - working with graphics processors, network technologies, and highly loaded systems. Therefore, CXL developers expect the new standard to be in demand among machine learning institutes and data center operators. Since the technology is “ sharpened ” for GPU, FPGA, ASIC and other accelerators, it will most likely not be used in the architecture of user PCs.
The IT community is of the opinion that the new standard may not be widely adopted. Since the industry is already enoughsimilar standards and specifications, for example CCIX and GenZ (we will talk about them below). A wide adaptation of the standard may be hindered by the model of its distribution. Although Compute Express Link is an open standard, only members of the consortium have access to its full specification . And while it is not clear whether they will compete with each other in the market after the release.
/ Wikimedia / BiomedNMR / CC BY-SA
Similar standards
As we mentioned above, CXL has several analogues, including GenZ and CCIX.
The GenZ bus specification, called the "possible successor to PCIe," was released in February 2018. About fifty large IT companies took part in its development. The purpose of creating the standard does not differ from the goals of CXL - to increase the speed of data exchange between the processor, memory and graphics cards.
Representatives of the consortium argue that Gen-Z bypasses the point-to-point communication limitation that is present in PCIe and accesses memory directly. The specification is already ready and is in the public domain on the consortium website.
CCIX is another consortium of whicheminent corporations are listed . The first specification of the standard of the same name was released in the summer of 2018. It is based on PCIe 4.0, which allows achieving a throughput of 25 GB / s.
The architecture concept based on the first CCIX specification was already implemented by Xilinx on its Versal FPGA chip . In the near future, other market players also plan to introduce CCIX, some of them have already submitted test implementations.
The future of the standard
At least two consortiums are already ahead of CXL in spec development speed. However, there is a chance that the advantages of the PCIe 5.0 standard will help CXL get ahead of the competition and become the industry standard for manufacturers of processors and heterogeneous systems. Devices based on this technology will help to speed up work with data in the data center and the cloud, and will find application in the development of AI systems and HPC solutions.
What else to read in our blog on Habré: