Current activity around MIPSfpga and not only


    There are several events and topics that I would like to share with the community. In a good way, for each one you can write a separate article, but the general lack of time makes us a bit foolish. Our topics today are:

    • MIPSfpga 2.0 release;
    • processor schoolMIPS and Summer School for Young Programmers in Novosibirsk;
    • seminar school on digital design and computer architecture in Tomsk;
    • Linux vanilla kernel launch on MIPSfpga-plus;
    • support for the Altera MAX10 ADC in MIPSfpga-plus;
    • MIPSfpga-plus logo.

    If the topic of MIPSfpga-plus is not indifferent to you, then at the end there is a small survey on what I should write (or not write) the next article. Your choice will help me navigate and prioritize. Welcome !

    MIPSfpga 2.0 Release

    2 years after the first release of MIPSfpga, Imagination Technologies released a second version of the package: MIPSfpga 2.0 [ L1 ].
    What you should pay attention to:

    • as before, MIPSfpga is presented not only as open source codes of an industrial processor core open under an academic license, but also as a set of educational materials, which also includes documentation and laboratory work. And this is wonderful, because complete with the book “Digital Circuitry and Computer Architecture” (H&H) [ L2 ], recently translated into Russian, we get a very high-quality and affordable set of theory and practice presented on the example of MIPS architecture;
    • at a recent symposium [ L3 ] in Toronto, Sarah Harris (one of the authors of H&H) presented a collective article [ L14 ], which provides a sufficiently detailed description of MIPSfpga 2.0, as well as an analysis of the spread of the Imagination Technologies educational initiative across universities.And (wow!) My name is even mentioned there in connection with activity in the MIPSfpga-plus project.
    • if the first release was mainly focused on how to assemble a system on a chip (SoC) based on MIPSfpga, then the second emphasis is shifted specifically to the processor itself:

    List of laboratory work

    1 Create a Project in Vivado or Quartus-II
    2 Learn how to compile, debug and run C programs
    3 Learn MIPS Assembly Programming system
    4 More C Programming Practice (optional)
    5 Expand the system to add 7-segment displays
    6 Expand the system to add a counter
    7 Expand the system to add a buzzer
    8 Expand the system to add an SPI-Light Sensor
    9 Expand the system to add a SPI-LCD
    10 Interact with peripherals using interrupts
    11 Build a DMA engine for transfers between peripherals
    12 Build a Data Encryption Standard (DES) engine
    13 Learn how to use the Performance Counters
    14 Execution of ADD and other arithmetic instruction
    15 Execution of AND and other logic instructions
    16 Execution of LW and other related instructions
    17 Execution of BEQ and other related instructions
    18 Learn how the Hazard Unit is implemented
    19 Learn how to use the CorExtend interface
    20 Introduction to the caches available in MIPSfpga
    21 Analyze the D $ and implement new configurations
    22 Cache Controller: Analyze a cache hit and miss
    23 Cache Controller: Analyze D $ management policies
    24 Cache Controller: Analyze the Store and Fill Buffers
    25 Implement an Instruction Scratchpad RAM

    • According to preliminary information, the core itself has not undergone any special changes, it’s the same MIPS microAptiv UP, on the basis of which, for example, Microchip PIC32MZ is built;
    • The focus on Xilinx during the construction of SoC in laboratory works remained unchanged. So, the general scheme of SoC used in laboratory work is as follows, which somewhat limits the launch on Altera-based boards:
      MIPSfpga Linux SoC

    Given that Digilent artificially limits the supply of its motherboards to non-FPGA Xilinx in Russia and Ukraine, the picture is not very pleasant. But here MIPSfpga-plus comes to our aid - an opensource project for building SoCs based on MIPSfpga with platform-independent peripherals [ L4 ]. For correct interaction with MIPSfpga 2.0, it may have to be slightly modified.

    schoolMIPS and Summer School for Young Programmers

    The Summer School of Young Programmers [ L5 ] has opened today in Novosibirsk . The school curriculum involves the division into workshops [ L6 ], one of which is focused on teaching Verilog and chip architecture. The children’s teacher will be Yuri Panchul YuriPanchul , who specially flew from the United States for this purpose.

    Workshop of chip architects

    Master: Yuri Punchul

    Digital hardware, from logic to its own processor

    Want to know how microchips are designed in modern devices - from the phone to the spaceship? Over the past 25 years, this has been done using the methodology of logical synthesis of code in hardware description languages. We will learn this technology in our workshop and apply it to design our own devices.

    We will start with the three key building blocks of digital electronics - a logic element, a clock signal and a D-trigger, memory for one bit of information. For clarity, we will master them in the old-fashioned way by connecting microcircuits with a small degree of integration on the breadboard to the wires.

    Then we will repeat the constructed circuits in the SystemVerilog hardware description language and model them on a simulator. But how can we translate them into microchips? After all, ordering a commercial microcircuit at a factory is very expensive? Fortunately, there are “tunable” programmable logic integrated circuits (FPGAs), boards with which we will use for our classes.

    In addition to exercises with arithmetic blocks and state machines, we will try to build a simple processor, similar in microarchitecture to the Mongoose-V processor inside the New Horizons spacecraft, which flew past Pluto a year ago.

    At the same time, we will study a little assembler programming, the concept of interrupts, compare our processor with industrial microcontrollers and built-in microprocessors, up to the EyeQ5 microprocessor for a self-propelled car, which is planned for release in 2020.

    This is cool, and to be honest, I envy these students a little - in my childhood this was not.
    Especially for this event, we wrote a small processor of MIPS architecture: schoolMIPS [ L7 ], which is planned to be used in the educational process. It is built by simplifying the processor of Sarah Harris, described in H&H [ L2 ]. Key Features:

    • Verilog Hardware Description Language
    • a subset of the MIPS architecture with instruction memory, with general purpose registers, but without data memory;
    • single-cycle microarchitecture;
    • minimum set of instructions, initially sufficient to calculate the Fibonacci number and integer square root in an iterative way;
    • maximally simplified microarchitecture and code for teaching purposes;
    • compilation of programs is carried out by means of MIPS toolchain.

    In the kit there is a small instruction and slides describing the construction of the processor core in a style similar to H&H [ L2 ].
    In addition to writing the processor, a fairly large-scale translation into Russian of various educational materials was performed. I will not touch on this topic, because I did not participate, I believe that Yuri YuriPanchul will write about this in the future.

    School-seminar on digital design and computer architecture in Tomsk

    From September 18 to 22, a seminar-school on digital design and computer architecture in the era of systems on a chip (SoC) and Internet technologies (IoT) will be held at the Tomsk State University. The preliminary program of the school and the list of participants are published on the site [ L8 ]. Your humble servant will also speak there: I plan to talk about AHB-Lite, connecting peripherals to MIPSfpga, working with SDRAM - this is from the scene. And unofficially we can discuss Linux, connecting a debugger and any code that I brought to MIPSfpga-plus. Come!

    Running Linux on MIPSfpga-plus

    Laboratory work MIPSfpga describes the launch of Linux on SoK, built using Xilinx-specific peripheral modules. Together with the problem with access to boards already mentioned above, this created some difficulties. The minimum required to run Linux OS are: MMU (included with MIPS fpga), sufficient memory and UART. However, most of the porting of the system has already been done by Imagination Technologies, the corresponding code is included in the main branch of the kernel [ L9 ]. Just a week ago, I managed to run Linux on the Terasic DE10-Lite and I won’t say that the necessary patch for this turned out to be very complicated.
    Key Features:

    • system configuration: FPGA Altera MAX10, SDRAM 64MB, MIPSfpga-plus, UART16550;
    • the kernel is loaded into memory using EJTAG [ L10 ];
    • mmc / sdcard is not yet supported, so there’s no need to talk about booting from a memory card. On the other hand, in the laboratory work of MIPSfpga, there is no talk about boot from a flash drive either.

    Boot log
    Linux version 4.12.2+ (stas@ubuntu) (gcc version 4.9.2 (Codescape GNU Tools 2016.05-03 for MIPS MTI Linux) ) #67      Wed Jul 19 00:07:19 MSK 2017
    CPU0 revision is: 00019e60 (MIPS M14KEc)
    MIPS: machine is terasic,de10lite
    Determined physical RAM map:
     memory: 04000000 @ 00000000 (usable)
    Initrd not found or empty - disabling initrd
    Primary instruction cache 4kB, VIPT, 2-way, linesize 16 bytes.
    Primary data cache 4kB, 2-way, VIPT, no aliases, linesize 16 bytes
    Zone ranges:
      Normal   [mem 0x0000000000000000-0x0000000003ffffff]
    Movable zone start for each node
    Early memory node ranges
      node   0: [mem 0x0000000000000000-0x0000000003ffffff]
    Initmem setup node 0 [mem 0x0000000000000000-0x0000000003ffffff]
    Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
    Kernel command line: console=ttyS0,115200
    PID hash table entries: 256 (order: -2, 1024 bytes)
    Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
    Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
    Memory: 60512K/65536K available (1827K kernel code, 97K rwdata, 320K rodata, 948K init, 184K bss, 5024K reserved     , 0K cma-reserved)
    clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 38225208935 ns
    sched_clock: 32 bits at 50MHz, resolution 20ns, wraps every 42949672950ns
    Console: colour dummy device 80x25
    Calibrating delay loop... 10.81 BogoMIPS (lpj=21632)
    pid_max: default: 32768 minimum: 301
    Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
    Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
    devtmpfs: initialized
    clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
    futex hash table entries: 256 (order: -1, 3072 bytes)
    clocksource: Switched to clocksource MIPS
    random: fast init done
    workingset: timestamp_bits=30 max_order=14 bucket_order=0
    Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
    console [ttyS0] disabled
    b0400000.serial: ttyS0 at MMIO 0xb0401000 (irq = 0, base_baud = 3125000) is a 16550A
    console [ttyS0] enabled
    Freeing unused kernel memory: 948K
    This architecture does not have kernel memory protection.
    mount: mounting devpts on /dev/pts failed: No such device
    mount: mounting tmpfs on /dev/shm failed: Invalid argument
    mount: mounting tmpfs on /tmp failed: Invalid argument
    mount: mounting tmpfs on /run failed: Invalid argument
    Starting logging: OK
    Initializing random number generator... done.
    Starting network: ip: socket: Function not implemented
    ip: socket: Function not implemented
    Welcome to MIPSfpga
    mipsfpga login: root
    Jan  1 00:00:09 login[43]: root login on 'console'
    # uname -a
    Linux mipsfpga 4.12.2+ #67 Wed Jul 19 00:07:19 MSK 2017 mips GNU/Linux
    # free -m
                 total       used       free     shared    buffers     cached
    Mem:            60          3         56          0          0          2
    -/+ buffers/cache:          0         59
    Swap:            0          0          0

    In the near future I plan to prepare a small HOWTO on how to reproduce these results. And I’ll probably write a great article after adding a module to work with mmc / sdcard in MIPSfpga-plus, finishing the bootloader and debugging everything that is necessary for an autonomous launch. If someone needs "right now" - let me know.

    MIPSfpga-plus and Altera MAX10 ADCs

    In June, he finished work on the integration of the ADC, which is on board the Altera MAX10, in MIPSfpga-plus. The corresponding code is added to the main branch of the project [ L11 ], with documentation [ L12 ] and an example [ L13 ]. The module, in fact, is a converter between the AHB-Lite bus and Avalon-ST, made taking into account the specifics of a particular ADC. It is very simple in architecture - tried to make its program interface as similar as possible to the Atmel ATmega88 microcontroller ADC.
    Of course, there were some pitfalls, as on the FPGA used in the Terasic DE10-Lite FPGA, 2 ADC channels are available (with independent sets of inputs on each); when wiring these inputs, the second channel was completely grounded, i.e. parallel operation of channels on DE10-Lite - impossible:

    Terasic DE10-Lite ADC pins

    I would like to believe that in academic projects MIPSfpga-plus will be used a little more often where before that, for the sake of the built-in ADC, it was necessary to take a microcontroller or configuration MAX10 + NIOS-II.
    Again, is there a need for a separate article where work with ADCs is discussed in detail? Or in order to understand, are you enough of the links I have already given to the source code of the module, example, and documentation?

    MIPSfpga-plus logo

    Do you think the MIPSfpga-plus project has matured enough to have its own recognizable logo? I, probably, having spent more than a dozen hours on it, I already want him to be associated with some kind of positive picture. For some reason, only Big Ukh from the cartoon of the same name comes to mind (see KDPV), it is possible because of its confederate, which is well associated with the initially educational focus of the project. And in principle, this character is deeply sympathetic to me.
    What do you think about this topic? Maybe you can offer some alternative option, or, suddenly, among the readers there is an artist who can portray a "cartoon character, vaguely reminiscent of the Big Ear, but not to the point of confusion"?


    The author thanks the team of translators of the textbook David Harris and Sarah Harris “Digital circuitry and computer architecture” [ L2 ], Imagination Technologies [ L1 ] for the academic license for the modern processor core and educational materials, as well as personally Yuri Panchul YuriPanchul for his work on promoting MIPSfpga. Special thanks to Alexander Romanov (HSE, MIEM) [ L15 ] for a sensible and meticulous approach to the schoolMIPS microarchitecture, as well as to all the participants in the Young Russian Chip Architects mailing list.


    [L1] - Press release on the release of MIPSfpga 2.0 ;
    [L2] - Digital circuitry and computer architecture ;
    [L3] - Workshop on Computer Architecture Education (Toronto) ;
    [L4] - The MIPSfpga-plus project on github ;
    [L5] - Summer School of Programmers (Novosibirsk) ;
    [L6] - Summer School of Programmers (Novosibirsk). Curriculum ;
    [L7] - Project schoolMIPS on github ;
    [L8] - School-seminar on digital design and computer architecture (Tomsk) ;
    [L9] - Support for MIPSfpga in the Linux kernel ;
    [L10] -MIPSfpga и внутрисхемная отладка;
    [L11] — MIPSfpga-plus. Модуль поддержки АЦП Altera MAX10;
    [L12] — MIPSfpga-plus. Модуль поддержки АЦП Altera MAX10. Документация;
    [L13] — MIPSfpga-plus. Модуль поддержки АЦП Altera MAX10. Пример;
    [L14] — Practical experiences based on MIPSfpga;
    [L15] — Профиль Александра Романова на сайте ВШЭ.

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    О чем написать в следующий раз

    • 30%перевод статьи Practical experiences based on MIPSfpga6
    • 25%подробная статья про интеграцию MIPSfpga и АЦП Altera MAX105
    • 30% article about running Linux on MIPSfpga in its current form 6
    • 15% do not get distracted by the scribble, better boot Linux with mmc / sdcard 3

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