For lovers of FPGAs, ASICs, architecture and microarchitecture - more about seminars and conveyors

    Colleagues: as you may already know, Imagination Technologies (known as a GPU developer inside the Apple iPhone + a successor to the Stanford / MIPS cult project) along with RUSNANO + MISiS + MSU + MIPT + MIET in Moscow, ITMO in St. Petersburg and Kiev activists from KPI and KSU - holds a series of seminars on the development of microcircuits and programming of embedded microprocessors. The closest of these seminars will be next week (October 18-20 in Alma-Ata). In this post - the current hourly schedule of seminars and a little aesthetic images of conveyors of embedded microprocessor cores, about the length, maximum frequency and energy consumption of which we will talk a little during the seminars.



    So the timetables:

    First, Alma-Ata.

    October 18-20, 2016 - Alma-Ata, Kazakh National Technical University named after K. I. Satpayev.
    The main organizer is the Department of Automation and Management of KazNITU, in partnership with Almaty Management University.
    The email for registering for the combined seminar on MIPSfpga and Connected MCU is seminar-kazntu@silicon-kazakhstan.com .

    Alma-Athens asked to do seminars in English, so here is a schedule of three-day seminars in English: Dates and contact information about seminars in Russia and Ukraine are provided in the post Chips from different angles: Nanometer ASIC, MIPSfpga and Connected MCU seminars in Russia, Ukraine and Kazakhstan . Briefly:











    The preliminary schedule of one-day seminars on MIPSfpga at MSU, MIPT, MIET, ITMO and KPI is lower. At the end there is information about a possible additional day, which theoretically could arise at Moscow State University in addition to the current schedule: About the Nanometer ASIC seminar, there has recently been a post ( habrahabr.ru/post/311662 ) and there will be another one, since the seminar can be done addition. The current schedule is http://edunano.ru/doc/6335690702352234538 . And now a few pipelines diagrams of embedded microprocessor cores optimized for a different balance of performance, maximum clock speed and power consumption. We will talk about this a bit in each of the seminars:











    A short conveyor, a low maximum clock frequency, but low power consumption: The





    conveyor is slightly longer, but a higher clock frequency is higher:



    But the processor is optimized for efficiency (reasonably high performance with low power consumption):





    Optimized for speed: superscalar with OoO:



    See you!


    Also popular now: