Intel Vision Accelerator - Deep Learning in every home
Let us briefly dwell on the topic of new Intel processors (this is quite a short while) and talk about machine vision and Deep Learning. In general, the topic of AI became common when discussing the prospects for the development of computer technology, and many, I think, noticed the following feature. Gradually, with the improvement of specialized hardware and software, AI elements are leaving the data centers with super-servers "in the field", becoming increasingly available technically and financially. Intel also sees this trend, and, in order to simplify the introduction of advanced technologies in everyday life, they offer vendors to take advantage of their new solution - Intel Vision Accelerator .
What is the Intel Vision Accelerator? This is a set of reference designs for accelerator boards, on the basis of which any electronics manufacturer can create its product with the necessary set of features. However, naturally, just design is not enough - you need an element base. Intel already has it - this is a specialized Movidius and FPGA Arria co-processor. What are the advantages of this approach?
- the possibility of inference of neural networks "in place";
- high performance on specialized tasks;
- high efficiency in terms of energy consumption, cost, etc .;
- full compatibility with the Open Visual Inference & Neural Network Optimization (OpenVINO) toolkit - a set of libraries, optimization tools and information resources for the development of software using machine vision and Deep Learning.
Let's compare these two platforms with reference to Deep Learning.
| Intel Vision Accelerator with Intel Movidius | Intel Vision Accelerator with Intel Arria | |
|---|---|---|
| Feature | High efficiency in terms of consumption and cost | Productive Integrated Solution |
| Application area | Classic neural networks | Additional optimization during deep learning using high-loaded networks |
| Use cases | Devices with size and consumption limitations, classic network topologies that can be optimized for ASIC | Servers of the middle and initial levels, environments that respond well to software optimization |
| Connection Interfaces | PCIe, mini-PCIe, M2 | PCIe |
| Number of video streams | From 1 to 16 per device | From 3 to 32 |
| Batch size | 1-4 | 1-144 |
| power usage | ~ 2 W | ~ 35 W |
| Topologies | Algorithms |
|---|---|
| GoogleNet ResNet – 18 ResNet – 50 ResNet – 101 SqueezeNet SqueezeNext VGG-16 Faster RCNN MobileNet Tiny Yolo | Face detection / recognition Classification of face attributes Hand tracking Sex and age detection Subject definition / subject tracking Behavior recognition and gestures Determination of abandoned objects Multipurpose tracking Definition of a letter / word , etc. |