UDB. What is it? Part 6. Status and Control Module

In past articles, translations of Cypress documentation, the operational automaton Datapath was very substantively considered. Gradually we move on to the study of other UDB modules, in particular, the management and status module.

General content of the cycle “UDB. What is this? ”
Part 1. Introduction. Pld.
Part 2. Datapath.
Part 3. Datapath FIFO.
Part 4. Datapath ALU.
Part 5. Datapath. Useful little things.
Part 6. Management and status module. (Current article)
Part 7. Timing and Reset Control Module
Part 8. UDB Addressing

21.3.3. Management and Status Module

A high-level view of the control module and status is shown in Figure 21-28. The status bits of the control register are transferred to trace resources, giving the program the ability to control the behavior of UDB. The status register receives data from the trace lines, so the program can monitor operations performed by UDB.


Figure 21-28. Registers of management and status.

The structure of the control module and status is shown in more detail in Figure 21-29. The main goal of this unit is to coordinate the interaction of the processor core program with the operation of the internal elements of UDB. However, due to the strong connection with the trace matrix, this block can be configured to perform other functions.


Figure 21-29. Control and status module.

Operating modes:

• Input status / the Status the Input . The status of lines wound up from outside can be entered and captured as status, after which the CPU or DMA is read.
• Output control / the Control the Output . The CPU or DMA can write data to the control register. This data will determine the state of the lines going to the trace resources.
• Parallel Input - Parallel to Datapath.
• Parallel Output - from the parallel output of Datapath.
• Counter Mode / Counter Mode . In this mode, the control register operates as a 7-bit decreasing counter with a programmable period and automatic reset. Trace channel inputs can be configured to control both on and reset of the counter. When this mode is activated, the functionality of the control register is not available.
• Synchronous / Sync-Mode . In this mode, the status register acts as a 4-bit dual synchronizer. When this mode is activated, the status register functionality is not available.

21.3.3.1 Status and Control Mode

When operating in control and status mode, this module acts as a status register, mask override register, and control register in the configuration shown in Figure 21-30.


Figure 21-30. Job management and status.

Status Register Operation

Each UDB has one 8-bit status register. The input to this register comes from any signal from a digital trace structure. The status register is destructible: it loses its state during sleep and after waking up has a value of 0x00. Each bit can be independently programmed to operate in one of two modes.

Table 21-19. Status Register.


An important feature of the status register clearing operation is that only cocked bits are cleared. This allows the remaining bits to continue capturing status to maintain process continuity.

Normal reading status

By default, the CPU transparently reads the status of the corresponding circuit. This mode can be used to read data latched inside UDB.

Sticky status with clear after reading

In this mode, the status register inputs are sampled on each control and status clock cycle. If the signal at a given clock is high, it is captured in the status bit and remains high, regardless of subsequent input states. When the CPU or DMA reads the status register, the bit is cleared. Clearing the status register is mode independent and occurs even when UDB clocking is disabled; it is based on bus timing and occurs as part of a read operation.

Latch status while reading

Figure 21-31 shows the structure of the status reading logic. The sticky status register is followed by a latch that latches the status register data and keeps it stable during the read cycle, regardless of the number of wait ticks in the current read operation.


Figure 21-31. The logic of reading status.

Interrupt generation

In most functions, interrupt generation is tied to the status bit parameters. As shown in Figure 21-31, this feature is built into the status register logic in the form of a masking operation and applying the OR operation to the status. Only the lower 7 bits of the status input can be used with the built-in interrupt generators. The most significant bit (Most Significant Bit, MSB) is usually used as the interrupt output and can be forwarded to the interrupt controller using digital tracing channels. In this configuration, the status of the interrupt request bit is read from the high status register bit.

21.3.3.2 Control Register Operation

Each UDB has one 8-bit control register available. It works as a standard read / write register on the system bus, where the output of these register bits is controlled by the lines of the digital trace structure.

The control register is destructible: it loses its state during sleep and after waking up has a value of 0x00.

Management Register Modes

Each bit can be configured in one of three modes. The configuration is specified by combining the bits of two 8-bit registers CTL_MD1 [7: 0] and CTL_MD0 [7: 0]. For example, {CTL_MD1 [0], CTL_MD0 [0]} controls the zero bit mode of the control register (see table 21-20).

Table 21-20. Control Register Zero Bit Mode

Direct control register mode

By default, the mode is direct. As shown in Figure 21-32, when the CPU or DMA is written to the control register, on the same cycle the output of the control register is sent directly to the trace line.


Figure 21-32. Direct control register mode.

Synchronous control register mode

In synchronous mode, as shown in Figure 21-33, the output of the control register is out of sync with the clock equal to the current clock of the control and status (Status and Control, SC). This allows you to control the output timing diagrams at the selected SC frequency, rather than at the bus clock frequency.


Figure 21-33. Synchronous control register mode.

Pulse mode control register

The pulse mode is similar to synchronous mode, since in it the control bit is re-sampled at the SC frequency; the pulse begins on the first SC clock cycle and follows the bus write cycle. The control bit output is set during one full SC clock cycle. At the end of this clock cycle, the control bit is automatically reset.

With this mode of operation, the program can write 1 to the control register bit to generate a pulse. After the bit is assigned the value 1, the program will read it as 1 until the pulse ends, after which it will be read as 0. After that, the program can write another 1 to start a new pulse. Thus, it will not be possible to give a pulse more often than on every second step of the SC signal.

Reset Management Register

The control register has two reset modes controlled by the EXT RES configuration bit, as shown in Figure 21-34. When EXT RES is 0 (default), in synchronous or pulse mode, the traced reset input resets the synchronized output, but not the control bit itself. When EXT RES is 1, the traced reset input resets both the control bit and the synchronized output.


Figure 21-34. Reset management register.

21.3.3.3 Parallel Input / Output Mode

In this mode, control and status tracing is connected to the parallel in and parallel out Datapath signals. To activate this mode, you need to cock the SC OUT configuration bits to select the parallel Datapath output. A connection to a parallel input is always available, however these trace connections are shared with the status register inputs, counter control inputs, and interrupt outputs.


Figure 21-35. Parallel I / O mode.

21.3.3.4 Counter Mode

As shown in Figure 21-36, when the unit operates in counter mode, a 7-bit decreasing counter is available for use both within operations within the UDB and for the needs of the program. The features of the meter include:

• 7-bit period register, (read / write).
• 7-bit account register, (read / write). Access is possible only when the counter is stopped.
• Automatically reloads the period in the account register when it reaches zero.
• The software-controlled control bit in the auxiliary control register CNT START, used to start and stop the counter. (It overlaps the ENABLE hardware signal and must be installed for the optional ENABLE hardware signal to function).
• Selectable bits of the trace channels of the optional dynamic counter control for the start and load functions:
  - EN, trace signal to start or stop counting.
  - LD, a traceable load signal that causes a period reload. When this signal is cocked, it overlaps the pending end signal. It is sensitive to the level, and while the signal is cocked, the period continues to load.
• A 7-bit counter can be sent to trace resources as sc_out [6: 0].
• An end-of-signal can enter trace resources as sc_out [7].
• In the “default” mode, the snap mode is used for the end signal. In alternative mode, it switches to combination mode.
• In default mode, the optional hardware EN signal, if used, must be set to enable the LD hardware signal to work. In alternative mode, the LD and EN hardware signals are independent.

Figure 21-36. Counter mode

Translator's note:
At about this point, I realized that I completely understand nothing from the document. Nowhere is this “default” and “alternative” modes described. After a long search, I managed to find some, but an example.
File: C: \ Program Files (x86) \ Cypress \ PSoC Creator \ 4.2 \ PSoC Creator \ psoc \ content \ CyComponentLibrary \ CyComponentLibrary.cylib \ bScanComp_v1_10 \ bScanComp_v1_10.v
Explaining code:

Same text:

    cy_psoc3_count7 #(.cy_period(Period),.cy_route_ld(0),.cy_route_en(1), .cy_alt_mode(1))
    ChannelCounter(
        /* input          */ .clock(clk_int),
        /* input          */ .reset(1'b0),
        /* input          */ .load(1'b0),
        /* input          */ .enable(enable_int),
        /* output [06:00] */ .count(count),
        /* output         */ .tc(tc_o)
    );

The very declaration of the component cy_psoc3_count7 I found only for the VHDL language, it seems that for Verilog it is built into the development tools. Now you know roughly where to look for the tuning bits in question.

Here we look at the mysterious bits, which are called either SC OUT CTL or SC_OUT_CTL, but their values ​​are not documented. I did not find them at all anywhere. It is clear from the text that they switch the STATUS_CONTROL component between modes. But in the previously mentioned VHDL file C: \ Program Files (x86) \ Cypress \ PSoC Creator \ 4.2 \ PSoC Creator \ warp \ lib \ lcpsoc3 \ cpsoc3.vhd

we see separately the counter already known to us

component cy_psoc3_count7
    generic(cy_period : std_logic_vector (6 downto 0) := "1111111";
            cy_init_value : std_logic_vector (6 downto 0) := "0000000";
     cy_route_ld : boolean := false;
     cy_route_en : boolean := false;
     cy_alt_mode : boolean := false);
    port (clock : in std_logic;
     reset : in std_logic;
     load : in std_logic;
     enable : in std_logic;
     count : out std_logic_vector (6 downto 0);
     tc : out std_logic);
end component;

separately - status and management

    attribute atomic_rtl of cy_psoc3_status : component is rtl_generic;
    attribute cpu_access of cy_psoc3_status : component is true;
component cy_psoc3_statusi
    generic(cy_force_order : boolean := false;
     cy_md_select : std_logic_vector (6 downto 0) := "0000000";
     cy_int_mask : std_logic_vector (6 downto 0) := "0000000");
    port (reset : in std_logic := '0';
     clock : in std_logic := '0';
     status : in std_logic_vector (6 downto 0);
     interrupt : out std_logic);
end component;
    attribute atomic_rtl of cy_psoc3_statusi : component is rtl_generic;
    attribute cpu_access of cy_psoc3_statusi : component is true;
component cy_psoc3_control
    generic(cy_init_value : std_logic_vector (7 downto 0) := "00000000";
     cy_force_order : boolean := false;
     cy_ctrl_mode_1 : std_logic_vector (7 downto 0) := "00000000";
     cy_ctrl_mode_0 : std_logic_vector (7 downto 0) := "00000000";
     cy_ext_reset : boolean := false);
    port (reset : in std_logic := '0';
     clock : in std_logic := '0';
     control : out std_logic_vector (7 downto 0));
end component;

separately - synchronizer

component cy_psoc3_sync
    port (clock : in std_logic := '0';
     sc_in : in std_logic;
     sc_out : out std_logic);
end component;

I repeat that Verilog does not have a version of these declarations at all (there are only behavioral models in the C: \ Program Files (x86) \ Cypress \ PSoC Creator \ 4.2 \ PSoC Creator \ warp \ lib \ sim directory, so I think that the bits setting modes are not accessible to simple programmers. When reading this section, you should keep this fact in mind. Something is given purely for reference, it is not subject to us programmers.

To enable counter mode, the counter output must be selected in the SC_OUT_CTI [1: 0] bits. In this mode, normal operation of the control register is not available. At the same time, the status register can be used for read operations, but you should not use it to generate an interrupt, since the mask mapping register is also used as a counter period register. The period register is not destroyed and retains its state after waking up. For a period of N measures, the value N-1 must be loaded into the period register. The value N = 1 (the period is zero) as the value of the frequency divider is not supported and will lead to a constant unit at the output of the TC (Terminal count, TC). The availability of SYNC mode depends on whether dynamic control (LD / EN) is used or not. If it is not used, it does not affect the SYNC mode. If used,

21.3.3.5 Sync Mode

As shown in Figure 21-37, the status register can operate as a 4-bit dual clock synchronized with the current SC_CLK value if the SYNC MD bit is set. This mode can be used to implement local synchronization of asynchronous signals (for example, GPIO inputs). In this case, the synchronized signals are selected from SC_IN [3: 0], the outputs are routed to the contacts SC_IO_OUT [3: 0], and SYNC MD automatically switches the contacts SC_IO to the output mode. In this mode, the normal operation of the status register is not available, and the sticky status bit mode is forcibly disabled, regardless of the mode control settings. This mode does not affect the control register. The counter can still be used, but with limitations. In this operating mode, dynamic inputs (LD / EN) cannot be used.


Figure 21-37. Synchronous mode.

21.3.3.6 Status and Control Clocking

The control and status registers require a clock selection in any of the following operating modes:

• status register with any bit in sticky mode with clearing after reading,
• control register in counter mode,
• synchronous mode.

Timing is assigned in the clock and reset module. See 21.3.4. Clock and reset control module.

21.3.3.7 Auxiliary Control Register

The auxiliary control register for reading and writing is a special register that controls hard-set UDB equipment. This register allows the CPU or DMA to dynamically control interrupts, FIFOs, and counter operation. The bits of the registers and their description are given below:

Clear FIFO0 and FIFO1 (FIFO0 Clear, FIFO1 Clear)

The FIFO0 CLR and FIFO1 CLR bits are used to reset the status of the corresponding FIFOs. When 1 is written to these bits, the state of the corresponding FIFO is reset. To continue FIFO operation, it is necessary to write 0. These bits remain cocked. FIFOs work as simple single-byte buffers with no status.

FIFO0 and FIFO1 Level (FIFO0 Level, FIFO1 Level)

The FIFO0 LVL and FIFO1 LVL bits set the level at which a 4-byte FIFO raises the bus status (when the bus reads or writes to FIFO). The FIFO bus status value depends on the configured direction, as shown in the table below.

Table 21-21. FIFO level control bits.

Interrupt Enable

When the status register generation logic is activated, the INT EN bit enables the generated interrupt signal to pass through.

Start counter / account? (Count Start)

The CNT START bit can be used to start and stop the counter (only available if the SC_OUT_CTL [1: 0] bits are configured for the counter output mode).

21.3.3.8 Summary of control and status registers

The table below summarizes the functions of the control and status registers. Please note that mask and control registers are combined with counters and period registers, and the value of these registers does not depend on the operating mode.

Table 21-22. A brief summary of the operation of the management and status registers

but. - note that in counter mode, the mask overlay register works as a period register and cannot work as a mask over register. Therefore, the interrupt output is not available when the counter mode is activated.

b. - note that in synchronization mode the status register is not available, and therefore it is impossible to use the mask overlay register. However, it can be used as a period register for counter mode.

To be continued…