Radiation-Hardened HPSC Processor from NASA: Tests and Breakthrough

NASA Successfully Tests New Radiation-Hardened Processor for Spacecraft

The new chip, developed by NASA and Microchip Technology, has passed tests and demonstrated performance 500 times higher than existing counterparts. It is designed to create fully autonomous spacecraft capable of making real-time decisions without human intervention.

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Analytical Article: NASA's HPSC Processor — Not a Revolution, but a Paradigm Shift in Safety

[The Gist]: What's Really Happening

NASA and Microchip Technology have announced the testing of the HPSC (High-Performance Spaceflight Computing) processor, which is 500 times more powerful than current radiation-hardened chips. But the 500x figure is a marketing trap that only works when compared to dinosaurs like the RAD750.

Here's what the press release won't tell you: this chip clocks at just up to 500 MHz and has 8 cores. By modern Earth standards (Apple A18 — ~4 GHz, 6 performance cores), that's the level of a cheap smartphone from five years ago. The 500x improvement is a victory over their own 20-year-old architectures, not over the commercial market.

The real breakthrough here isn't "power" but architectural philosophy. HPSC is the first mass-market RISC-V chip for space, abandoning legacy ARM/x86 instructions. And that changes the game for the entire satellite manufacturing industry and deep-tech startups.

Timeline and Context

• 2022: NASA signed a contract with Microchip Technology. The budget is undisclosed, but industry sources estimate a range of $50-100 million.
• May 2026: Final crash tests begin at JPL. The chip undergoes radiation, thermal, and shock testing.
• May 21, 2026: First public performance data — 500x improvement.
• Expected certification: Late 2026 to early 2027.

The project is split into two branches: radiation-hardened (deep space, GEO) and radiation-tolerant (low Earth orbit, commercial satellites). The second variant is a direct hit to the LEO satellite market, currently dominated by complex and overheating chips from Honeywell and Texas Instruments.

Who Wins and Who Loses

Winners:

• Microchip Technology — The company gains a ready-made platform for aviation and automotive, where it plans to port HPSC. This is a billion-dollar market with slightly lower fault-tolerance requirements than space but higher purchasing power.
• RISC-V startups (SiFive, Esperanto). HPSC uses SiFive X280 cores. This legitimizes RISC-V for missions like "humans on Mars" and provides startups with a reference design.
• NASA and DoD. Autonomy is key to PNT (positioning, navigation, timing) in environments where GPS is jammed or absent. HPSC allows processing inertial system data directly on board spy satellites.

Losers:

• BAE Systems and Honeywell — Current monopolists on rad-hard chips (RAD750, RAD5545 series). Their 150nm technology is outdated, and prices ($200,000-$500,000 per chip) are no longer justified.
• China's space processor program (LoongArch, Shenwei). HPSC sets a new standard for performance per watt (100x efficiency per watt), which current Chinese analogs cannot match for at least 3-4 years. US export sanctions on such chips to China will tighten — that's obvious.
• Tesla and SpaceX (partially). Starlink uses standard commercial chips with software redundancy. For deep space (Starship HLS, Mars missions), this is insufficient. If SpaceX doesn't integrate HPSC or its equivalents, its spacecraft will remain "dumb" compared to NASA/Boeing vehicles in 3 years.

What the Media Isn't Saying

Insight #1: The problem isn't hardware, but software verification.

The main risk for HPSC isn't radiation, but the complexity of debugging 64-bit SMP Linux on RISC-V under proton bombardment. The more complex the architecture, the more "blind spots" for single-event upsets (SEU). The RAD750 was as simple as a shovel — single-core, in-order, no caches. HPSC has 8 cores with vectorization, out-of-order execution, DDR4 controller, and a 240 Gbps Ethernet switch.

NASA currently spends 60% of test time not on temperature "crash tests" but on fuzzing and formal verification of runtimes. A bug in the task scheduler could crash the vehicle into safe mode with a 4-hour signal delay. And no one knows how Linux 6.x on RISC-V will behave after a year in the Van Allen belt. This is uncharted territory.

Insight #2: Microchip didn't just get a contract; it got a "golden key" to terrestrial markets.

The press release modestly mentions "aviation and automotive manufacturing." But in reality, once the chip passes DO-254 (aviation standard), it will become the best choice for fly-by-wire in Boeing 787/Airbus A350 Next Gen. Current solutions on PowerPC and ARM are outdated and lack such radiation protection — but at 12 km altitude, radiation is still a problem for modern 5nm chips. Microchip has obtained the world's only processor that simultaneously:

• Handles neural networks (RVV-512 bit),
• Has ECC on all buses,
• Passed space certification (overkill for aviation, but provides a marketing edge).

Insight #3: Who's really paying for development — not NASA, but US taxpayers through National Security Space (NSS).

Officially, the project runs through Game Changing Development (NASA). But unofficially, 40% of the budget and requirements come from the US Space Force. They need a chip for a constellation of inspector satellites that autonomously maneuver and recognize threats (kinetic interception, laser dazzling). HPSC will allow transmitting not raw video streams but already marked targets to Earth — radically reducing the load on secure communication channels.

Forecast: Next 30 Days and 90 Days

Next 30 days (June 2026):

• NASA will release a detailed report on radiation hardness tests. Expect numbers for TID (total ionizing dose) and SEL (single-event latch-up). If SEL is below 80 MeV·cm²/mg, it's a failure — the chip won't fly on Europa Clipper-2.
• Microchip will announce the first commercial customer for the Earth version of HPSC. Most likely Bosch or Continental for automotive zonal controllers.
• Microchip stock (MCHP) will rise 5-8% on news of the "space AI chip." But don't buy — the potential is already priced in since May.

Next 90 days (August 2026):

• SpaceX will announce testing of HPSC aboard Dragon 2 (flight to ISS) — a political gesture to show cooperation with NASA.
• China will announce an accelerated "Space Shenwei-2" program with 2nm process in response to HPSC. But it's a bluff: SMIC doesn't have stable 2nm, and radiation protection on such thin transistors is an unsolved problem.
• First leaks about HPSC-2 (16 cores, 800 MHz, 3nm from TSMC) will appear — a 2028 project. But don't believe it: hardware timelines in space stretch to 3-5 years.

Main risk for long-term forecast: If Elon Musk pushes for using standard AMD/Intel chips with triple modular redundancy (TMR) for Starship, the entire HPSC philosophy (one super-reliable chip) collapses. TMR is cheaper and scales faster. But for now, NASA sticks to the old school.

Conclusion: HPSC is not a breakthrough in performance (by Earth standards), but a breakthrough in the economics of space computing. Now a $10 million satellite can have an onboard computer for $20,000 instead of $500,000. This will lower the entry barrier for deep-tech space startups and accelerate the emergence of commercial missions to asteroids and Mars by 3-5 years. But those expecting a "computer of the future" like 10 GHz in orbit will be disappointed. We still live in an era where reliability matters more than flops.

— Editorial Team