March 21, 2019 at 13:00Linux Foundation will deal with open source chips
The Linux Foundation has opened a new direction - the CHIPS Alliance. Within the framework of this project, the organization will develop a free RISC-V instruction system and technologies for creating processors based on it. We will tell in more detail what is happening in this area. / photo Gareth Halfacree CC BY-SA
Patches that protect against Meltdown and Specter, in some cases, reduce server performance by 50%. At the same time, new variations of vulnerabilities associated with speculative execution of commands still appear. One of them became known in early March - information security experts dubbed it Spoiler. This situation affects the discussion of the need to review existing hardware solutions and approaches to their development. In particular, Intel is already preparing a new architecture for its processors, not affected by Meltdown and Specter.
They did not stand aside in the Linux Foundation. The organization launched its own initiative - the CHIPS Alliance - whose members will be engaged in the development of processors based on RISC-V.
The search IT giant transferred to the open source platform for testing processors based on RISC-V. The solution randomly generates commands that allow you to check the operability of the device: they test transition processes, call stacks, CSR registers, etc.
For example, this is how the class looks for a simple test of arithmetic instructions:
According to the developers, the platform differs from analogues in that it allows you to consistently check all the components of the chip, including the memory block.
This is a network protocol from WD that provides cache coherency when transferring data over Ethernet. OmniXtend allows you to exchange messages directly with the processor cache and is used to connect various accelerators: GPU or FPGA. It is also suitable for creating systems based on several RISC-V chips.
The protocol is already supported by SweRV chips focused on data processing in data centers. SweRV is a 32-bit, dual-pipeline superscalar processor based on a 28-nanometer process technology. Each pipeline has nine levels, which makes it possible to load and execute several commands simultaneously. The device operates at a frequency of 1.8 GHz.
A solution from SiFive, which was founded by the developers of RISC-V technology. Rocket Chip is a RISC-V processor core generator in Chisel. It is a collection of parameterized libraries that are used to create SoC .
As for Chisel , this is a Scala-based hardware description language. It generates low-level code on Verilog, which is suitable for processing on ASIC and FPGA. Thus, it allows the use of OOP principles in the development of RTL .
Experts say the Linux Foundation initiative will make the processor market more democratic and open to new players. IDC notes that the growing popularity of such projects will have a positive effect on the development of machine learning technologies and AI systems in general.
/ photo Fritzchens Fritz PD
The development of open source processors will also reduce the cost of designing custom chips. However, this will only happen if the Linux Foundation community manages to attract enough developers.
Other organizations are developing projects related to open hardware. An example would be the CXL consortium, which introduced the Compute Express Link standard in mid-March. The technology is an analog of OmniXtend and also connects CPU, GPU, FPGA. For data exchange, the standard uses the PCIe 5.0 bus.
Another project involved in the development of processor technologies is MIPS Open, which appeared in December 2018. The initiative was created by the startup Wave Computing. Developers plan to open up the latest 32-bit and 64-bit MIPS instruction sets to the IT community. The start of the project is expected in the coming months.
In general, the open source approach is becoming generally accepted not only for software, but also for hardware. Such projects are supported by large companies. Therefore, we can expect that in the near future more devices will appear on the market, which are based on open hardware standards.
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Why the CHIPS Alliance appeared
Patches that protect against Meltdown and Specter, in some cases, reduce server performance by 50%. At the same time, new variations of vulnerabilities associated with speculative execution of commands still appear. One of them became known in early March - information security experts dubbed it Spoiler. This situation affects the discussion of the need to review existing hardware solutions and approaches to their development. In particular, Intel is already preparing a new architecture for its processors, not affected by Meltdown and Specter.
They did not stand aside in the Linux Foundation. The organization launched its own initiative - the CHIPS Alliance - whose members will be engaged in the development of processors based on RISC-V.
What projects are already developing
The CHIPS Alliance members list includes Google, Western Digital (WD) and SiFive. Each of them presented its own developments. Let's talk about some of them.
RISCV-DV
The search IT giant transferred to the open source platform for testing processors based on RISC-V. The solution randomly generates commands that allow you to check the operability of the device: they test transition processes, call stacks, CSR registers, etc.
For example, this is how the class looks for a simple test of arithmetic instructions:
class riscv_arithmetic_basic_test extends riscv_instr_base_test;
`uvm_component_utils(riscv_arithmetic_basic_test)
`uvm_component_new
virtual function void randomize_cfg();
cfg.instr_cnt = 10000;
cfg.num_of_sub_program = 0;
cfg.no_fence = 1;
cfg.no_data_page = 1'b1;
cfg.no_branch_jump = 1'b1;
`DV_CHECK_RANDOMIZE_WITH_FATAL(cfg,
init_privileged_mode == MACHINE_MODE;
max_nested_loop == 0;)
`uvm_info(`gfn, $sformatf("riscv_instr_gen_config is randomized:\n%0s",
cfg.sprint()), UVM_LOW)
endfunction
endclass
According to the developers, the platform differs from analogues in that it allows you to consistently check all the components of the chip, including the memory block.
OmniXtend Protocol
This is a network protocol from WD that provides cache coherency when transferring data over Ethernet. OmniXtend allows you to exchange messages directly with the processor cache and is used to connect various accelerators: GPU or FPGA. It is also suitable for creating systems based on several RISC-V chips.
The protocol is already supported by SweRV chips focused on data processing in data centers. SweRV is a 32-bit, dual-pipeline superscalar processor based on a 28-nanometer process technology. Each pipeline has nine levels, which makes it possible to load and execute several commands simultaneously. The device operates at a frequency of 1.8 GHz.
Rocket Chip Generator
A solution from SiFive, which was founded by the developers of RISC-V technology. Rocket Chip is a RISC-V processor core generator in Chisel. It is a collection of parameterized libraries that are used to create SoC .
As for Chisel , this is a Scala-based hardware description language. It generates low-level code on Verilog, which is suitable for processing on ASIC and FPGA. Thus, it allows the use of OOP principles in the development of RTL .
Alliance Prospects
Experts say the Linux Foundation initiative will make the processor market more democratic and open to new players. IDC notes that the growing popularity of such projects will have a positive effect on the development of machine learning technologies and AI systems in general.
/ photo Fritzchens Fritz PD
The development of open source processors will also reduce the cost of designing custom chips. However, this will only happen if the Linux Foundation community manages to attract enough developers.
Similar projects
Other organizations are developing projects related to open hardware. An example would be the CXL consortium, which introduced the Compute Express Link standard in mid-March. The technology is an analog of OmniXtend and also connects CPU, GPU, FPGA. For data exchange, the standard uses the PCIe 5.0 bus.
Another project involved in the development of processor technologies is MIPS Open, which appeared in December 2018. The initiative was created by the startup Wave Computing. Developers plan to open up the latest 32-bit and 64-bit MIPS instruction sets to the IT community. The start of the project is expected in the coming months.
In general, the open source approach is becoming generally accepted not only for software, but also for hardware. Such projects are supported by large companies. Therefore, we can expect that in the near future more devices will appear on the market, which are based on open hardware standards.
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