Ternary counters: mod 3 circuits on binary elements

Divide-by-3 Frequency Counters: Semimodular Designs with Binary Logic

Ternary counters divide the input pulse frequency by 3. These circuits are built entirely from binary logic gates and belong to the class of semimodular sequential structures. The divide-by-3 ratio is chosen as the closest to a power of two, minimizing differences from standard binary counters and simplifying the principles for arbitrary dividers.

Sequential operation is ensured by a transition completion indicator that prevents race conditions and guarantees determinism.

Counting Flip-Flops as the Building Block

The simplest sequential counting flip-flop using three gates is described by these equations:

X = X Z ∨ Y ¬Z
Y = Y ¬Z ∨ ¬X Z
Z = X Y ∨ ¬X ¬Y

Element X holds its state when Z=1 and takes the input value when Z=0. Y latches when Z=0 and inverts X when Z=1. Z activates when X=Y (after X triggers) and resets when X≠Y (after Y), serving as a transition completion indicator.

A perfect implementation with RS flip-flops avoiding the forbidden 11 state (Fig.1c) turns the circuit into a single-clock counting flip-flop. Breaking the jumper creates the input and transition indication. Self-oscillation provides the second clock cycle.

Known single-clock flip-flop variants (Fig.2):

• Harvard-style with AND-NOT and upper indicator.
• Master-slave using dual-polarity flip-flops.
• Simplified versions with AND-OR-NOT and OR-AND-NOT.

Binary Mod-3 Counter

The base is a two-bit sequential counter using Harvard flip-flops (Fig.3a). Overflow (state 3) is redirected to 1 by adding an inverter: the overflow signal plus its inverse blocks the indicator and input until the transition completes (Fig.3b).

Advantages:

• Versatility for k≠2ⁿ.
• Adjustable divide ratio (like the 74LS161 equivalent).

Drawback: Slowdown on the 'limping' transition after overflow.

Ring Distribution Circuits

The prototype is a ring of three inverters (Fig.4a). Clock synchronization and transition indication use inverting G-flip-flops (C-elements): output 1(0) when all inputs are 0(1), otherwise memory.

The ring cycles between state groups (two 1s + zero / two 0s + one). The indicator (AND-OR) triggers on group changes, generating a clock 3x faster than the ring elements (Fig.4b).

Perfect implementation (Fig.4c) — two-clock version on flip-flop arms, serving as a positional counter.

Tristable Flip-Flops in Counters

Bistable RS flip-flops are replaced by tristable ones: lower/upper in the Harvard flip-flop (Fig.5a) using three AND-NOT gates each. Key features:

• Two 1s in stable states, three in transient.
• Reset: 0 on inputs of gates with 1 on outputs.

Key Takeaways

• Semimodular designs with binary gates enable divide-by-3 without specialized ternary logic.
• The Z indicator is crucial for sequencing, preventing races in rings and counters.
• Binary foundations offer universality: from classic 74-series to modern FPGAs.
• G-flip-flops (C-elements) are ideal for asynchronous distributors.
• Tristable elements boost bit depth without extra gates.

— Editorial Team