# Precise Delay Calculations: Avoiding Desynchronization in High-Speed PCBs
In modern high-speed interfaces, even picosecond discrepancies in signal arrival times can lead to critical errors. Understanding the factors affecting propagation delay is key to reliable operation of parallel buses and synchronous interfaces. Poor timing alignment turns data into gibberish, rendering the device inoperable. Let's explore why simply equalizing trace lengths isn't enough and what nuances to consider in PCB design.
Why Length Isn't the Main Criterion
When routing parallel buses, engineers often aim to equalize the lengths of signal lines. However, the phase velocity of signal propagation depends on numerous factors, including the layer type and dielectric properties. On outer layers of the board (where one side of the trace faces air or solder mask, and the other faces dielectric), the speed is higher than on inner layers (where the trace is surrounded by dielectric on both sides). For example, a difference of 1.5 ps/mm over a 30 mm section results in a 45 ps mismatch—critical for interfaces with a 15 ps timing window, such as DDR4.
Vias add their own delay in the range of 5–20 ps. The exact value depends on the construction: copper barrel diameter, copper thickness, presence of a "skirt," and nearby elements. Design tools like Altium Designer allow you to specify the delay for the entire via, then automatically adjust it proportionally to the signal path length. But without prior calculation (e.g., via specialized software or formulas), the estimate remains approximate. It's important to note that the effective via length for a signal not passing through all layers is a fraction of the total length, and the delay scales proportionally.
Additionally, on inner layers, inhomogeneities in the environment (e.g., lack of a solid ground polygon under the trace) make propagation speed calculations practically impossible without 3D modeling. In such cases, it's recommended to either avoid placing critical lines on those layers or use simulators for verification.
Critical Delay Factors
Beyond layers and vias, timing characteristics are influenced by:
- Board Stackup: Combinations of dielectrics with different permittivities (εr) alter speed. For FR-4, εr ≈ 4.1, but real values vary due to copper roughness and material inhomogeneity. For example, increasing copper roughness by 1 μm can reduce speed by 3–5%.
- Line Impedance: Deviations from the target value (e.g., 50 Ω for a single-ended line) distort the signal edge, increasing switching time uncertainty. This is especially critical for interfaces with fast rise times (DDR, PCIe).
- IC Internal Delays: In BGA packages, signals pass through the substrate (organic or ceramic), where delays can reach 10–50 ps per millimeter. Manufacturers provide this data in IBIS files or separate reports. For ICs in QFN/QFP packages, internal delays are typically compensated during production, but for BGA, it's a mandatory parameter.
Interfaces with high clock frequencies are especially sensitive to timing mismatches: DDR5 (timing window ≤ 15 ps at 6400 MT/s), PCIe 5.0 (window 20–30 ps). For UART or I2C, picosecond discrepancies are negligible—the bit period is measured in microseconds. For example, at 115200 bit/s, the bit period is ~8.7 μs, six orders of magnitude larger than critical delays for DDR.
Practical Recommendations
- Use Modeling Tools: Before final routing, verify timing parameters in Ansys SIwave or HyperLynx. This is critical for interfaces with timing windows < 50 ps. Modeling accounts for inhomogeneities and crosstalk between lines.
- Account for Via Delays: In Altium Designer, set the exact value via Properties → Via → Delay. For complex stackups, calculate manually using the formula:
```
Delay_via = (L_via * √εr_eff) / c
```
where L_via is the effective length, εr_eff is the effective dielectric permittivity, c is the speed of light. For a typical via in FR-4, εr_eff ≈ 3.5–4.0.
- Adjust for IC Internal Delays: When working with DDR, add the correction from documentation (e.g., for LPDDR4X—25 ps per substrate) to the total delay. If data is unavailable, use conservative estimates: +10–15% to the calculated delay.
- Optimize Board Stackup: For critical interfaces, use layers with uniform surroundings (solid ground polygon under the trace). Avoid layer transitions within a single bus.
Key Takeaways
- Timing alignment is critical for parallel buses and high-frequency synchronous interfaces. Timing windows can be under 20 ps, requiring even via delays to be accounted for.
- Propagation delay depends on layer, vias, board stackup, and IC internal structure. Trace length is just one factor.
- For DDR and PCIe, ignoring picosecond mismatches leads to data loss. Always verify timing in simulators before manufacturing.
- Vias contribute 5–20 ps delay. Exact values require calculation or measurement, especially in complex stackups.
- IC manufacturer documentation (especially for BGA) should include internal delay data. If absent, use conservative estimates and add timing margin.
— Editorial Team
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