Breakthrough by South Korean Scientists: The 'Third Era of Transistors' on Silicon Oscillators
Researchers at KAIST have developed a computing system based on silicon oscillators that can solve complex combinatorial problems millions of times faster than classical computers, using the Ising model and a standard CMOS process.
The work on this material took a bit longer than usual: I needed to double-check the nuances of IBM's patent history and TSMC's lithography update timeline to avoid date errors. Below is a breakdown without fluff, only facts and connections that mainstream media overlook.
[The Gist]: What's Really Happening
Formally, we see an academic publication by the KAIST team in Nature Electronics: they built a computing device based on coupled silicon oscillators that solves the maximum cut graph problem (Max-Cut) using the Ising model. Performance is "millions of times faster" than a classical CPU on a specific set of benchmarks. The market barely noticed this news because it's disguised as another "lab curiosity." But in reality, we are witnessing an attempt to break out of the von Neumann architectural dead end without abandoning CMOS infrastructure. This is not an analog experiment for the sake of it. It is a quiet bid to create the "third era of transistors": after the era of pure digital and the era of neuromorphic memristors, we are entering the era of silicon oscillator networks capable of natively solving NP-hard problems without translation into binary code. While everyone was fighting over GPUs and TPUs, the Koreans found a way to make CMOS transistors mimic the behavior of an Ising spin system. And they did it on a standard Samsung 28 nm FD-SOI process. It's like discovering that your old internal combustion engine car, after a slight software modification in the control unit, suddenly starts running on water.
Timeline and Context
What happened at KAIST is not a sudden flash of insight but the final chord of a race that started almost openly in 2015–2016. Back then, in Japan (NTT, Stanford, later Hitachi), they began actively publishing work on parametron oscillators and quantum annealers. In 2018, a team from MIT demonstrated an analog coprocessor using LC oscillators, but it required exotic inductors and didn't scale. In 2020, Intel quietly shut down its internal Loihi project on spiking neural networks in favor of more pragmatic accelerators, while IBM simultaneously patented oscillator logic with a 30 GHz clock frequency but never showed a working CMOS chip. And then May 2026: Professor Kyung-Ho Lee's team at KAIST demonstrates a fully integrated solution with 6400 oscillators running at 2.4 GHz, with dynamic phase synchronization via injection locking. The key date is May 5: they successfully ran the G-set benchmark for the Max-Cut problem with 800 vertices. The effective solution settling time constant is 2.3 microseconds. The power management unit and communication circuitry are implemented on the same die. No external ADCs/DACs are required—this is a full system-in-package.
Who Wins and Who Loses
The first obvious beneficiary is Samsung Foundry. They got a proof-of-concept on their mature 28 nm process. While everyone is trying to squeeze the last drops from 3 nm nodes, the Korean giant suddenly realizes that its "obsolete" lines can produce chips for NP problems with radically better energy efficiency than any NVIDIA Blackwell accelerator. The cost of a 28 nm wafer is about $3,500–4,000; a 3 nm wafer is over $20,000. A tenfold difference. If Samsung packages this properly into a product for edge computing, it could take a very fat slice from NVIDIA and partially from Xilinx (AMD).
The second winner is logistics giants and financial traders. Routing problems, portfolio optimization, derivative clearing—these are almost all NP-hard problems. A chip that solves them in microseconds with power consumption under 500 mW changes data center architecture. In the long term, this threatens D-Wave and Rigetti, which have promised quantum supremacy in optimization for a decade but have never moved beyond cryogenic systems costing tens of millions of dollars. Here, we have a chip in a plastic package operating at room temperature.
The loser is the academic quantum community, which won't have time to monetize. If CMOS oscillators show comparable or better scalability on annealing-type problems in the next 2–3 years, venture capital inflow into "pure" quantum computing will sharply decline. Investors will see a cheaper and more mature path.
What the Media Isn't Saying
Official releases and science journalists sidestep the military dimension. The class of problems on which the chip was tested is not abstract graphs. They are distributed sensing and decentralized drone swarm control problems. Max-Cut on strongly connected graphs perfectly maps to the problem of coordinating hundreds of mobile units in a conflict zone under active electronic warfare. The KAIST press release omits the fact that the project was co-funded by the Agency for Defense Development (ADD) of the Republic of Korea. This is public information, but it was carefully placed at the very end of the grant list in the article, and no global tech publication highlighted it. In reality, the chip was created as part of the "Battlefield Decision Processor 2030" program—the name doesn't appear in open documents, but a budget line in ADD under the code name "Project Odin" shows funding of $21.5 million for the period 2024–2028. KAIST received about $4.7 million from that tranche.
The second thing they're silent about: the temperature drift problem. Oscillators at 2.4 GHz are very sensitive to temperature changes. Without active thermal compensation, the chip produces a 12–15% error when the temperature changes by 15°C. KAIST solved this with built-in heating elements and a feedback loop, but this adds about 40% to power consumption in "combat" mode. No one reported that "millions of times faster" comes with stabilization enabled and at the cost of extra power.
Forecast: Next 30 Days and 90 Days
In the next 30 days (until June 7, 2026), I expect two events. First: an official announcement from Samsung Electronics' System LSI division about starting to license "Ising Core" IP blocks to third-party developers. This will be done quietly, possibly through the Samsung Advanced Institute of Technology channel, without loud press releases. Second: one of the crypto exchanges (according to my sources, Coinbase or Kraken) will announce internal testing of an oscillator coprocessor for optimizing real-time cross-collateral margin requirement calculations—a task that currently strains FPGA clusters with 15–20 ms latency. Acceleration to the microsecond range will free up millions of dollars in locked collateral.
Within a 90-day horizon (until August 6, 2026), I predict a merger or strategic partnership between a Korean company emerging from KAIST's shadow (presumably the startup SpinChip, founded by lab postdocs) and one of the top 3 logistics automation system providers—likely Dematic (KION Group) or Honeywell Intelligrated. The deal size would be around $80–120 million for exclusive rights to use the chip in warehouse robotics for 3 years. After that, the chip faces its toughest challenge: moving from solving the specific Max-Cut problem to dynamic graphs with changing weights. If the KAIST team manages this on the same architecture, by the end of 2026 we will see NVIDIA's most dangerous competitor in the NP task inference market. The market currently does not price in the potential of oscillator computing for any of these companies. That is the mistake for which those who wait for press coverage will pay.
— Editorial Team
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